PIC24FJ256GB106T-I/PT Microchip Technology, PIC24FJ256GB106T-I/PT Datasheet - Page 6

• Manufacturer Part Number: PIC24FJ256GB106T-I/PT
• Description: IC PIC MCU FLASH 256K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GB106T-I/PT

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• For Use With: DM240011 - KIT STARTER MPLAB FOR PIC24F MCUMA240014 - MODULE PLUG-IN PIC24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC24FJ256GB106T-I/PTTR

PIC24FJ256GB110 FAMILY
15. Module: UART (IrDA)
16. Module: UART (IrDA)
17. Module: I
DS80369K-page 6
When the UART is operating in 8-bit mode
(PDSEL<1:0> = 0x) and using the IrDA endec
(IREN = 1), a framing error may occur when
transmitting a data payload of 00h.
Work around:
None.
Affected Silicon Revisions
When the UART is operating in 9-bit mode
(PDSEL<1:0> = 1x) and using the IrDA endec
(IREN = 1), the module will incorrectly transmit
10 bits when transmitting data payloads of 00h or
80h.
Work around:
None.
Affected Silicon Revisions
Under certain circumstances, a module operating
in Master mode may Acknowledge its own com-
mand addressed to a slave device. This happens
when the following occurs:
• 10-Bit Addressing mode is used (A10M = 1)
• The I
In these cases, the Master also Acknowledges the
address command and generates an erroneous I
slave interrupt, as well as the I
Work around
Several options are available:
• When using 10-Bit Addressing mode, make
A3
A3
X
X
address bits (I2CADD<9:8>) as the addressed
slave module
certain that the master and slave devices do not
share the same 2 MSbs of their addresses.
2
A5
A5
C Master has the same two upper
2
C™ Module (Master Mode)
2
C master interrupt.
2
C
18. Module: I
If this cannot be avoided:
• Clear the A10M bit (I2CxCON<10> = 0) prior to
• Read the ADD10 bit (I2CxSTAT<8>) to check
Affected Silicon Revisions
Under certain circumstances, a module operating
in Slave mode, may not respond correctly to some
of the special addresses reserved by the I
protocol. This happens when the following occurs:
• 10-Bit Addressing mode is used (A10M = 1)
• Bits, A<7:1>, of the slave address
In these cases, the Slave module Acknowledges
the command and triggers an I
does not copy the data into the I2CxRCV register
or set the RBF bit.
Work around
Do not set bits, A<7:1>, of the module’s slave
address equal to ‘1111xxx’ or ‘0000xxx’.
Affected Silicon Revisions
A3
A3
performing a Master mode transmit.
for a full 10-bit match whenever a slave I
interrupt occurs on the master module.
X
(I2CADD<7:1>) fall into the range of the
reserved 7-bit address ranges: ‘1111xxx’ or
‘0000xxx’.
X
A5
A5
2
C Module (Slave Mode)
 2010 Microchip Technology Inc.
2
C slave interrupt; it
2
C
2
C