PIC16C73B-04E/SP Microchip Technology, PIC16C73B-04E/SP Datasheet - Page 26
![IC MCU OTP 4KX14 A/D PWM 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC16C73B-04E/SP
Manufacturer Part Number
PIC16C73B-04E/SP
Description
IC MCU OTP 4KX14 A/D PWM 28DIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16C63A-04SP.pdf
(184 pages)
4.PIC16C63A-04SP.pdf
(10 pages)
5.PIC16C63A-04SP.pdf
(10 pages)
Specifications of PIC16C73B-04E/SP
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
PIC16C63A/65B/73B/74B
4.3
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLATH register. On any RESET, the upper bits of the
PC will be cleared. Figure 4-3 shows the two situations
for the loading of the PC. The upper example in the fig-
ure shows how the PC is loaded on a write to PCL
(PCLATH<4:0>
ure shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH<4:3>
FIGURE 4-3:
4.3.1
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read" (AN556).
4.3.2
The PIC16CXX family has an 8-level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed, or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN,RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
DS30605C-page 26
PC
PC
12
12 11 10
2
PCL and PCLATH
PCH
5
PCLATH<4:3>
PCH
COMPUTED GOTO
STACK
PCLATH
PCLATH<4:0>
8
PCLATH
8
PCH). The lower example in the fig-
7
7
LOADING OF PC IN
DIFFERENT SITUATIONS
PCL
PCL
PCH).
11
8
0
0
Instruction with
PCL as
Destination
ALU
GOTO,CALL
Opcode <10:0>
4.4
PIC16CXX devices are capable of addressing a contin-
uous 8K word block of program memory. The CALL and
GOTO instructions provide only 11 bits of address to
allow branching within any 2K program memory page.
When executing a CALL or GOTO instruction, the upper
2 bits of the address are provided by PCLATH<4:3>.
When doing a CALL or GOTO instruction, the user must
ensure that the page select bits are programmed, so
that the desired program memory page is addressed. If
a return from a CALL instruction (or interrupt) is exe-
cuted, the entire 13-bit PC is popped from the stack.
Therefore, manipulation of the PCLATH<4:3> bits are
not required for the return instructions (which POPs the
address from the stack).
Example 4-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that PCLATH is saved and restored by the Interrupt
Service Routine (if interrupts are used).
EXAMPLE 4-1:
SUB1_P1
Note 1: There are no status bits to indicate stack
Note 1: The contents of PCLATH are unchanged
ORG
BSF
CALL
:
:
ORG
:
:
:
RETURN
Program Memory Paging
2: There are no instructions/mnemonics
2: PCLATH<4> is not used in these
0x500
PCLATH,3 ;Select page 1 (800h-FFFh)
SUB1_P1
0x900
overflow or stack underflow conditions.
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW, and RETFIE
instructions, or the vectoring to an inter-
rupt address.
after a return or RETFIE instruction is
executed. The user must set up PCLATH
for any subsequent CALL’s or GOTO’s
PICmicro
PCLATH<4> as a general purpose read/
write bit is not recommended, since this
may affect upward compatibility with
future products.
®
CALL OF A SUBROUTINE
IN PAGE 1 FROM PAGE 0
;Call subroutine in
;page 1 (800h-FFFh)
;page 1 (800h-FFFh)
;called subroutine
;page 1 (800h-FFFh)
;return to Call subroutine
;in page 0 (000h-7FFh)
2000 Microchip Technology Inc.
devices.
The
use
of