DSPIC30F4011-20E/PT Microchip Technology, DSPIC30F4011-20E/PT Datasheet - Page 94
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DSPIC30F4011-20E/PT
Manufacturer Part Number
DSPIC30F4011-20E/PT
Description
IC DSPIC MCU/DSP 48K 44TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F4012-30ISO.pdf
(238 pages)
2.DSPIC30F4012-30ISO.pdf
(18 pages)
3.DSPIC30F4012-30ISO.pdf
(6 pages)
4.DSPIC30F4012-30ISO.pdf
(16 pages)
5.DSPIC30F4012-30ISO.pdf
(22 pages)
6.DSPIC30F4011-30IP.pdf
(228 pages)
Specifications of DSPIC30F4011-20E/PT
Program Memory Type
FLASH
Program Memory Size
48KB (16K x 24)
Package / Case
44-TQFP, 44-VQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
30
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
30
Data Ram Size
2 KB
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Data Rom Size
1024 B
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature
- 40 C
Package
44TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
9-chx10-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F401120EPT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F4011-20E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F4011-20E/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
dsPIC30F4011/4012
14.7
Since the QEI module can function as a quadrature
encoder interface, or as a 16-bit timer, the following
section describes operation of the module in both
modes.
14.7.1
When the CPU is placed in the Idle mode, the QEI mod-
ule will operate if the QEISIDL bit (QEICON<13>) = 0.
This bit defaults to a logic ‘0’ upon executing POR and
BOR. For halting the QEI module during the CPU Idle
mode, QEISIDL should be set to ‘1’.
14.7.2
When the CPU is placed in the Idle mode and the QEI
module is configured in the 16-bit Timer mode, the
16-bit timer will operate if the QEISIDL bit (QEI-
CON<13>) = 0. This bit defaults to a logic ‘0’ upon
executing POR and BOR. For halting the timer module
during the CPU Idle mode, QEISIDL should be set
to ‘1’.
If the QEISIDL bit is cleared, the timer will function
normally as if the CPU Idle mode had not been
entered.
DS70135G-page 94
QEI Module Operation During CPU
Idle Mode
QEI OPERATION DURING CPU IDLE
MODE
TIMER OPERATION DURING CPU
IDLE MODE
14.8
The quadrature encoder interface has the ability to
generate an interrupt on occurrence of the following
events:
• Interrupt on 16-bit up/down position counter
• Detection of qualified index pulse or if CNTERR
• Timer period match event (overflow/underflow)
• Gate accumulation event
The QEI Interrupt Flag bit, QEIIF, is asserted upon
occurrence of any of the above events. The QEIIF bit
must be cleared in software. QEIIF is located in the
IFS2 register.
Enabling an interrupt is accomplished via the respec-
tive Enable bit, QEIIE. The QEIIE bit is located in the
IEC2 register.
rollover/underflow
bit is set
Quadrature Encoder Interface
Interrupts
© 2010 Microchip Technology Inc.