DSPIC30F2023-30I/PTD32 Microchip Technology, DSPIC30F2023-30I/PTD32 Datasheet - Page 136
![IC DSPIC MCU/DSP 12K 44-TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
DSPIC30F2023-30I/PTD32
Manufacturer Part Number
DSPIC30F2023-30I/PTD32
Description
IC DSPIC MCU/DSP 12K 44-TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.AC164335.pdf
(286 pages)
2.DM300023.pdf
(22 pages)
3.DM300023.pdf
(18 pages)
4.DSPIC30F2011-20ISO.pdf
(66 pages)
5.DSPIC30F2011-20IP.pdf
(26 pages)
6.DSPIC30F1010-30ISO.pdf
(26 pages)
7.DSPIC30F1010-30ISO.pdf
(50 pages)
Specifications of DSPIC30F2023-30I/PTD32
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
Q4035438
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- AC164335 PDF datasheet
- DM300023 PDF datasheet #2
- DM300023 PDF datasheet #3
- DSPIC30F2011-20ISO PDF datasheet #4
- DSPIC30F2011-20IP PDF datasheet #5
- DSPIC30F1010-30ISO PDF datasheet #6
- DSPIC30F1010-30ISO PDF datasheet #7
- Current page: 136 of 286
- Download datasheet (5Mb)
dsPIC30F1010/202X
12.24 PWM Current-Limit Pins
Each PWM generator can select its own current-limit
input source from up to12 current-limit/Fault pins. In the
FCLCONx registers, each PWM generator has control
bits (CLSRC<3:0>) that specify the source for its cur-
rent-limit input signal. Additionally, each PWM genera-
tor has a CLIEN bit in the PWMCONx register that
enables the generation of current-limit interrupt
requests. Each PWM generator has an associated
Fault polarity bit CLPOL in the FCLCONx register.
Figure 12-21 is a diagram of the PWM Current-Limit
control logic.
The current-limit pins actually serve two different pur-
poses. They can be used to implement either Current-
Limit PWM mode or Current Reset PWM mode.
1.
2.
FIGURE 12-21:
DS70178C-page 134
CMP1x
CMP2x
CMP3x
CMP4x
SFLT1
SFLT2
SFLT3
SFLT4
IFLT2
IFLT4
When the CLIEN bit is set in the PWMCONx
registers, the PWMxH,L outputs are forced to
the values specified by the CLDAT<1:0> bits in
the IOCONx register, if the selected current-limit
input signal is asserted.
When the CLMOD bit is zero AND the XPRES
bit in the PWMCONx register is ‘01’ AND the
PWM generator is in Independent Time Base
mode (ITB = 1), then a current-limit signal
resets the time base for the affected PWM gen-
erator. This behavior is called Current Reset
mode, which is used in some Power Factor
Correction (PFC) applications.
Analog Comparator
Module
PWM CURRENT-LIMIT CONTROL LOGIC DIAGRAM
Independent Fault # 2
Independent Fault # 4
Analog Comparator 1
Analog Comparator 2
Analog Comparator 3
Analog Comparator 4
Shared Fault # 1
Shared Fault # 3
Shared Fault # 2
Shared Fault # 4
Generator
PWMx
PWM Period
CLMOD
Reset
‘0000’
‘0001’
‘0010’
‘0011’
‘1000’
‘1001’
‘1010’
‘1011’
‘1101’
‘1111’
EN
CLSRC<3:0>
Preliminary
MUX
XPRES
EN
12.24.1
The state of the PWM current-limit conditions is avail-
able on the CLSTAT bits in the PWMCONx registers.
The CLSTAT bits display the current-limit IRQ flag if
the CLIEN bit is set. If current-limit interrupts are not
enabled, then the CLSTAT bits display the status of the
selected current-limit inputs in positive logic format.
When the current-limit input pin associated with a
PWM generator is not used, these pins become
general purpose I/O or interrupt input pins.
The current-limit pins are normally active high. If set to
‘1’, the CLPOL bit in FCLCONx registers inverts the
selected current-limit input signal to active high.
The interrupts generated by the selected current-limit
signals are combined to create a single interrupt
request signal to the interrupt controller, which has its
own interrupt vector, interrupt flag bit, interrupt enable
bit and interrupt priority bits associated with it.
The Fault pins are also readable through the PORT I/O
logic when the PWM module is enabled. This allows
the user to poll the state of the Fault pins in software.
PWMxH,L
CLDAT<1:0>
Signals
CURRENT-LIMIT INTERRUPTS
2
2
0
1
© 2006 Microchip Technology Inc.
MUX
CLSTAT
2
PWMxH,L
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