PIC24FJ256GA110-E/PT Microchip Technology, PIC24FJ256GA110-E/PT Datasheet - Page 33
![IC PIC MCU FLASH 256KB 100-TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
PIC24FJ256GA110-E/PT
Manufacturer Part Number
PIC24FJ256GA110-E/PT
Description
IC PIC MCU FLASH 256KB 100-TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ128GA008-IPT.pdf
(12 pages)
2.PIC24FJ128GA106-IPT.pdf
(14 pages)
3.PIC24FJ128GA106-IPT.pdf
(330 pages)
4.PIC24FJ128GA106-IPT.pdf
(52 pages)
5.PIC24FJ256GA106-IPT.pdf
(59 pages)
6.PIC24FJ128GA110-EPT.pdf
(310 pages)
Specifications of PIC24FJ256GA110-E/PT
Program Memory Type
FLASH
Program Memory Size
256KB (85.5K x 24)
Package / Case
100-TFQFP
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
85
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
85
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA240015 - BOARD MCV PIM FOR 24F256GADM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC164333 - MODULE SKT FOR PM3 100QFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ256GA110-E/PT
Manufacturer:
FREESCALE
Quantity:
3 100
Company:
Part Number:
PIC24FJ256GA110-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
4.6.4
PIC24FJXXXGA1/GB1 family devices provide two
complimentary methods to protect application code
from overwrites and erasures. These also help to pro-
tect the device from inadvertent configuration changes
during run time. Additional information is available in
the product data sheet.
4.6.4.1
For all devices in the PIC24FJXXXGA1/GB1 families,
the on-chip program memory space is treated as a
single block, known as the General Segment (GS).
Code protection for this block is controlled by one Con-
figuration bit, GCP. This bit inhibits external reads and
writes to the program memory space. It has no direct
effect in normal execution mode.
Write protection is controlled by the GWRP bit in the
Configuration Word. When GWRP is programmed to
‘0’, internal write and erase operations to program
memory are blocked.
4.6.4.2
In addition to global General Segment protection, a
separate subrange of the program memory space can
be individually protected against writes and erases.
This area can be used for many purposes where a
separate block of write and erase-protected code is
needed, such as bootloader applications. Unlike
common boot block implementations, the specially pro-
tected segment in PIC24FJXXXGA1/GB1 devices can
be located by the user anywhere in the program space,
and configured in a wide range of sizes.
Code segment protection provides an added level of
protection to a designated area of program memory by
disabling the NVM safety interlock whenever a write or
erase address falls within a specified range. It does not
override general segment protection controlled by the
GCP or GWRP bits. For example, if GCP and GWRP
are enabled, enabling segmented code protection for
the bottom half of program memory does not undo
general segment protection for the top half.
© 2007 Microchip Technology Inc.
Note:
CODE-PROTECT CONFIGURATION
BITS
Bulk Erasing in ICSP mode is the only way
to reprogram code-protect bits from an ON
state (‘0’) to an Off state (‘1’).
GENERAL SEGMENT
PROTECTION
CODE SEGMENT PROTECTION
PIC24FJXXXGA1/GB1
4.7
Exiting Program/Verify mode is done by removing V
from MCLR, as shown in Figure 4-6. The only require-
ment for exit is that an interval, P16, should elapse
between the last clock and program signals on PGCx
and PGDx before removing V
FIGURE 4-6:
MCLR
V
PGDx
PGCx
DD
Exiting Enhanced ICSP Mode
PGDx = Input
EXITING ENHANCED
ICSP™ MODE
V
P16
IH
IH
.
P17
V
IH
DS39907A-page 33
IH