ATMEGA645V-8MUR Atmel, ATMEGA645V-8MUR Datasheet
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ATMEGA645V-8MUR
Specifications of ATMEGA645V-8MUR
Related parts for ATMEGA645V-8MUR
ATMEGA645V-8MUR Summary of contents
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... I/O and Packages – 53/68 Programmable I/O Lines – 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP • Speed Grade: – ATmega325V/ATmega3250V/ATmega645V/ATmega6450V: • 4MHz @ 1.8 - 5.5V 8MHz @ 2.7 - 5.5V – Atmel ATmega325/3250/645/6450: • 8MHz @ 2.7 - 5.5V 16MHz @ 4.5 - 5.5V • Temperature range: – ...
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Pin Configurations Figure 1-1. Pinout ATmega3250/6450 1 DNC 2 (RXD/PCINT0) PE0 3 (TXD/PCINT1) PE1 4 (XCK/AIN0/PCINT2) PE2 5 (AIN1/PCINT3) PE3 (USCK/SCL/PCINT4) PE4 6 7 (DI/SDA/PCINT5) PE5 8 (DO/PCINT6) PE6 9 (CLKO/PCINT7) PE7 10 VCC 11 GND 12 DNC 13 ...
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Figure 1-2. Pinout ATmega325/645 DNC 1 (RXD/PCINT0) PE0 2 (TXD/PCINT1) PE1 3 (XCK/AIN0/PCINT2) PE2 4 (AIN1/PCINT3) PE3 5 (USCK/SCL/PCINT4) PE4 6 (DI/SDA/PCINT5) PE5 7 (DO/PCINT6) PE6 8 (CLKO/PCINT7) PE7 9 (SS/PCINT8) PB0 10 (SCK/PCINT9) PB1 11 (MOSI/PCINT10) PB2 12 (MISO/PCINT11) ...
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... Overview The Atmel ATmega325/3250/645/6450 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the Atmel ATmega325/3250/645/6450 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. ...
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... Self-Programmable Flash on a monolithic chip, the Atmel Atmel ATmega325/3250/645/6450 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The Atmel ATmega325/3250/645/6450 is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. ...
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Pin Descriptions The following section describes the I/O-pin special functions. 2.3 Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7..PA0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ...
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...
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XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.3.14 XTAL2 Output from the inverting Oscillator amplifier. 2.3.15 AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It ...
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... Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. ...
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... AVR CPU Core 6.1 Overview This section discusses the Atmel CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 6.2 Architectural Overview Figure 6-1. In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data ...
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... The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis- ters, SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the Atmel ATmega325/3250/645/6450 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used ...
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Status Register The Status Register contains information about the result of the most recently executed arithme- tic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is ...
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Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 6.5 General Purpose Register File The Register File is optimized for the ...
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Figure 6-3. X-register Y-register Z-register In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 6.6 Stack Pointer The Stack is mainly used for storing ...
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MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 6-4. 1st Instruction Execute 2nd Instruction Execute 3rd Instruction Execute Figure 6-5 on ...
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When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt ...
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When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. Assembly Code Example sei sleep; enter sleep, waiting for interrupt ; note: will enter sleep ...
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... Flash is organized as 16/32K x 16. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The Atmel ATmega325/3250/645/6450 Program Counter (PC) is 14/15 bits wide, thus addressing the 16/32K program memory locations ...
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... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 2,048 bytes of internal data SRAM in the Atmel ATmega325/3250/645/6450 are all accessi- ble through all these addressing modes. The Register File is described in Register File” ...
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... Figure 7-3. 7.3 EEPROM Data Memory The Atmel ATmega325/3250/645/6450 contains 1/2K bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Regis- ters, the EEPROM Data Register, and the EEPROM Control Register ...
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... Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel ATmega325/3250/645/6450 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions ...
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... Read/Write Initial Value • Bits 7:4 – Reserved Bits These bits are reserved bits in the Atmel ATmega325/3250/645/6450 and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt ...
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Bit 2 – EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM ...
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Table 7-1. Symbol EEPROM write (from CPU) The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts glob- ally) so that no interrupts ...
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Assembly Code Example EEPROM_read: C Code Example unsigned char EEPROM_read(unsigned int uiAddress 7.5.4 GPIOR2 – General Purpose I/O Register 2 Bit 0x2B (0x4B) Read/Write Initial Value 7.5.5 GPIOR1 – General Purpose I/O Register 1 Bit 0x2A (0x4A) Read/Write ...
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System Clock and Clock Options 8.1 Clock Systems and their Distribution Figure 8-1 on page 26 of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being ...
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Asynchronous Timer Clock – clk The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter ...
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Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be con- figured for use as an On-chip Oscillator, as shown in crystal or a ceramic resonator may be used. C1 and C2 ...
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Table 8-4. CKSEL0 Note: 8.4 Low-frequency Crystal Oscillator To use a 32.768 kHz watch crystal as the clock source for the device, the low-frequency crystal Oscillator must be selected by setting the CKSEL Fuses to ...
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This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 8-7 on page hardware loads the pre-programmed calibration value into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. The accuracy ...
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... CKOUT Fuse is programmed. 8.8 Timer/Counter Oscillator Atmel ATmega325/3250/645/6450 share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1 and XTAL2. This means that the Timer/Counter Oscillator can only be used when the calibrated internal RC Oscillator is selected as system clock source. The Oscillator is optimized for use with a 32 ...
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... System Clock Prescaler The Atmel ATmega325/3250/645/6450 system clock can be divided by setting the Clock Prescale Register” on page when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...
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The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the range. 8.10.2 CLKPR – Clock ...
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Table 8-11. CLKPS3 2570M–AVR–04/11 ATmega325/3250/645/6450 Clock Prescaler Select CLKPS2 CLKPS1 CLKPS0 ...
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Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s ...
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Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is ...
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Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept ...
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When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in ...
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Register Description 9.9.1 SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 0x33 (0x53) Read/Write Initial Value • Bits – SM2:0: Sleep Mode Select Bits 2, 1, ...
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... Read/Write Initial Value • Bits 7:4 - Reserved bits These bits are reserved bits in Atmel ATmega325/3250/645/6450 and will always read as zero. • Bit 3 - PRTIM1: Power Reduction Timer/Counter1 Writing logic one to this bit shuts down the Timer/Counter1 module. When Timer/Counter1 is enabled, operation will continue like before the shutdown. ...
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... SUT and CKSEL Fuses. The dif- ferent selections for the delay period are presented in 10.2 Reset Sources The Atmel ATmega325/3250/645/6450 has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • ...
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Figure 10-1. Reset Logic BODLEVEL [1..0] 10.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined below the detection level. The POR circuit can be used to ...
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... Figure 10-4. External Reset During Operation 10.5 Brown-out Detection Atmel ATmega325/3250/645/6450 has an On-chip Brown-out Detection (BOD) circuit for moni- toring the V the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as ...
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... Figure 10-6. Watchdog Reset During Operation 10.7 Internal Voltage Reference Atmel ATmega325/3250/645/6450 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 10.7.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used ...
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... Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the Atmel ATmega325/3250/645/6450 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to ...
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Table 10-2. WDP2 The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so ...
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Safety Level 1 In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any restriction. A timed sequence is needed when changing the Watchdog Time-out period or disabling ...
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... Read/Write Initial Value • Bits 7:5 – Reserved Bits These bits are reserved bits in the Atmel ATmega325/3250/645/6450 and will always read as zero. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...
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... Interrupts This section describes the specifics of the interrupt handling as performed in Atmel ATmega325/3250/645/6450. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 11.1 Interrupt Vectors in Atmel ATmega325/3250/645/6450 Table 11-1. Vector No (3) 24 (3) 25 Note: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see port – ...
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... Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 11-2. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in Atmel ATmega325/3250/645/6450 is: Addre ss 0x000 0 0x000 2 0x000 4 0x000 ...
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A 0x002 C 0x002 E 0x003 0 ; 0x003 2 0x003 3 0x003 4 0x003 5 0x003 6 0x003 7 2570M–AVR–04/11 ATmega325/3250/645/6450 jmp USI_OVF jmp ANA_COMP jmp ADC jmp EE_RDY jmp ...
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When the BOOTRST Fuse is unprogrammed, the Boot section size set to 4K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and ...
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When the BOOTRST Fuse is programmed, the Boot section size set to 4K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and ...
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Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is ...
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External Interrupts The External Interrupts are triggered by the INT0 pin or any of the PCINT30..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT30..0 pins are configured as outputs. This feature provides ...
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Figure 12-1. Pin Change Interrupt 12.2 Register Description 12.2.1 EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control. Bit (0x69) Read/Write Initial Value • Bit 1, 0 – ISC01, ...
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EIMSK – External Interrupt Mask Register Bit 0x1D (0x3D) Read/Write Initial Value • Bit 7 – PCIE3: Pin Change Interrupt Enable 3 When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set ...
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Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter- natively, the flag can be cleared by writing a logical one to it. This bit is reserved bit in ATmega325/645 and will always be read as ...
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Bit 7:0 – PCINT23:16: Pin Change Enable Mask 23..16 Each PCINT23:16 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT23:16 is set and the PCIE2 bit in EIMSK is set, pin change interrupt ...
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I/O-Ports 13.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with ...
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Functions” on page nate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 13.2 Ports as General Digital I/O The ...
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The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin ...
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Figure 13-3. Synchronization when Reading an Externally Applied Pin value INSTRUCTIONS 2570M–AVR–04/11 SYSTEM CLK XXX SYNC LATCH PINxn r17 ATmega325/3250/645/6450 XXX in r17, PINx 0x00 t pd, max t pd, min 0xFF 63 ...
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Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the ...
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Assembly Code Example C Code Example unsigned char i; Note: 13.2.5 Digital Input Enable and Sleep Modes As shown in Schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, ...
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Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin enable ...
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Table 13-2 ure 13-5 in the modules having the alternate function. Table 13-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate the ...
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Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 13-3. Port Pin PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 The alternate pin configuration is as follows: • OC2A/PCINT15, Bit 7 OC2, ...
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OC1A/PCINT13, Bit 5 OC1A, Output Compare Match A output: The PB5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDB5 set (one)) to serve this ...
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Table 13-4 shown in MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. Table 13-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 13-5. Signal Name PUOE PUOV DDOE ...
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Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 13-6. Port Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 The alternate pin configuration is as follows: • INT0 – Port D, ...
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Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 13-8. Port Pin PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 • PCINT7 – Port E, Bit 7 PCINT7, Pin Change Interrupt Source ...
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XCK/AIN0/PCINT2 – Port E, Bit 2 XCK, USART External Clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the USART oper- ates in ...
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Table 13-10. Overriding Signals for Alternate Functions in PE3:PE0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: 13.3.4 Alternate Functions of Port F The Port F has an alternate function as analog input for ...
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TDO, ADC6 – Port F, Bit 6 ADC6, Analog to Digital Converter, Channel 6 TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be ...
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Table 13-13. Overriding Signals for Alternate Functions in PF3:PF0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 13.3.5 Alternate Functions of Port G The alternate pin configuration is as follows: Table 13-14. Port G Pins ...
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Table 13-15. Overriding Signals for Alternate Functions in PG4 and PG3 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 13.3.6 Alternate Functions of Port H Port H is only present in ATmega3250/6450. The alternate pin ...
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PCINT20 – Port H, Bit 4 PCINT20, Pin Change Interrupt Source 20: The PH4 pin can serve as an external interrupt source. • PCINT19 – Port H, Bit 3 PCINT19, Pin Change Interrupt Source 19: The PH3 pin can ...
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Table 13-18. Overriding Signals for Alternate Functions in PH3:0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 13.3.7 Alternate Functions of Port J Port J is only present in ATmega3250/6450. The alternate pin configuration is ...
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PCINT27 – Port J, Bit 3 PCINT27, Pin Change Interrupt Source 27: The PE27 pin can serve as an external interrupt source. • PCINT26 – Port J, Bit 2 PCINT26, Pin Change Interrupt Source 26: The PE26 pin can ...
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Table 13-21. Overriding Signals for Alternate Functions in PH3:0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 13.4 Register Description 13.4.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 4 ...
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PORTB – Port B Data Register Bit 0x05 (0x25) Read/Write Initial Value 13.4.6 DDRB – Port B Data Direction Register Bit 0x04 (0x24) Read/Write Initial Value 13.4.7 PINB – Port B Input Pins Address Bit 0x03 (0x23) Read/Write Initial ...
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PIND – Port D Input Pins Address Bit 0x09 (0x29) Read/Write Initial Value 13.4.14 PORTE – Port E Data Register Bit 0x0E (0x2E) Read/Write Initial Value 13.4.15 DDRE – Port E Data Direction Register Bit 0x0D (0x2D) Read/Write Initial ...
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DDRG – Port G Data Direction Register Bit 0x13 (0x33) Read/Write Initial Value 13.4.22 PING – Port G Input Pins Address Bit 0x12 (0x32) Read/Write Initial Value 13.4.23 PORTH – Port H Data Register Bit (0xDA) Read/Write Initial Value ...
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Timer/Counter0 with PWM 14.1 Features Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module. The main features are: • Single Compare Unit Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse ...
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The definitions in Table 14-1. BOTTOM MAX TOP 14.2.2 Registers The Timer/Counter (TCNT0) and Output Compare Register (OCR0A) are 8-bit registers. Inter- rupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register ...
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Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 14-2 shows a block diagram of the counter and its surroundings. Figure 14-2. Counter Unit Block Diagram Signal description (internal signals): count direction clear ...
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Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM01:0 bits and Compare Output mode (COM0A1:0) bits. The max and bottom sig- nals are used by the Waveform Generator for handling the ...
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The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff- ering is disabled. The double buffering synchronizes the update ...
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Figure 14-4. Compare Match Output Unit, Schematic The general I/O port function is overridden by the Output Compare (OC0A) from the Waveform Generator if either of the COM0A1:0 bits are set. However, the OC0A pin direction (input or out- put) ...
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Normal Mode The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum ...
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The waveform generated will have a maximum frequency when OCR0A is set to zero (0x00). The waveform frequency is defined by the following clk_I/O equation: The N variable represents the ...
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In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0A1:0 to ...
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Figure 14-7. Phase Correct PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches ...
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The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. 14.8 Timer/Counter Timing Diagrams The ...
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Figure 14-11 Figure 14-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- clk clk (clk TCNTn (CTC) OCRnx OCFnx 14.9 Register Description 14.9.1 TCCR0A – Timer/Counter Control Register A Bit 0x24 (0x44) Read/Write Initial Value • Bit ...
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Table 14-2. Mode Note: • Bit 5:4 – COM01:0: Compare Match Output Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides ...
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Table 14-5. COM0A1 Note: • Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 14-6. CS02 ...
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The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC0A pin. 14.9.4 ...
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Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (f clock source. The ...
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Oscillator source (crystal, resonator, and capacitors) tolerances recommended that maximum frequency of an external clock source is less than f An external clock source can not be prescaled. Figure 15-1. Prescaler for Timer/Counter0 ...
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Timer/Counter1 16.1 Features The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e., Allows 16-bit PWM) • Two independent Output Compare Units ...
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Figure 16-1. 16-bit Timer/Counter Block Diagram Note: 16.2.1 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Regis- ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are ...
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Compare Units” on page 111. Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input ...
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The same temporary register is shared between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is written by the CPU, the ...
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The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_ReadTCNT1: C Code Example unsigned ...
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The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNT1: C Code Example void ...
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Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 16-2 Figure 16-2. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk TOP BOTTOM The 16-bit counter is mapped ...
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The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 16.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can ...
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TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is written ...
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I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). 16.7 Output Compare Units The 16-bit comparator continuously compares ...
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PWM pulses, thereby making the out- put glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer ...
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Secondly the COM1x1:0 bits control the OC1x pin output source. schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the ...
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A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits. 16.9 Modes ...
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Figure 16-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define ...
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The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the max- imum resolution is 16-bit ...
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When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next ...
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OCR1A set to MAX). The PWM resolu- tion in bits can be calculated by using the following equation: In phase correct PWM mode the counter is incremented until the counter value ...
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TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period ...
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OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: In phase and frequency correct PWM mode the counter is incremented until the counter value matches either ...
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Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively ...
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Figure 16-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f Figure 16-12 frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by ...
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Figure 16-13. Timer/Counter Timing Diagram, with Prescaler (f and ICF n 16.11 Register Description 16.11.1 TCCR1A – Timer/Counter1 Control Register A Bit (0x80) Read/Write Initial Value • Bit 7:6 – COM1A1:0: Compare Output Mode for Unit A • Bit 5:4 ...
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Table 16-3 PWM mode. Table 16-3. COM1A1/COM1B1 Note: Table 16-4 correct or the phase and frequency correct, PWM mode. Table 16-4. COM1A1/COM1B1 Note: • Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B ...
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Table 16-5. Waveform Generation Mode Bit Description WGM12 WGM11 Mode WGM13 (CTC1) (PWM11 ...
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When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap- ture function is disabled. • Bit 5 – Reserved ...
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A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. 16.11.4 TCNT1H and TCNT1L – Timer/Counter1 ...
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The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. ...
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Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B (OCR1B). Note that a Forced Output Compare (FOC1B) strobe ...
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Timer/Counter2 with PWM and Asynchronous Operation 17.1 Features Timer/Counter2 is a general purpose, single compare unit, 8-bit Timer/Counter module. The main features are: • Single Compare Unit Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, ...
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Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A) are 8-bit registers. Inter- rupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask ...
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Figure 17-2. Counter Unit Block Diagram Signal description (internal signals): count direction clear clk top bottom Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select ...
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Figure 17-3. Output Compare Unit, Block Diagram The OCR2A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. ...
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The setup of the OC2A should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2A value is to use the Force Output Com- pare (FOC2A) strobe bit in ...
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Compare Output Mode and Waveform Generation The Waveform Generator uses the COM2A1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2A1 tells the Waveform Generator that no action on the OC2A Register ...
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Figure 17-5. CTC Mode, Timing Diagram TCNTn OCnx (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be ...
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PWM mode is shown in togram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2A and TCNT2. Figure 17-6. Fast PWM Mode, ...
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Phase Correct PWM Mode The phase correct PWM mode (WGM21 provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM ...
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The PWM frequency for the output when using phase correct PWM can be calcu- lated by the following equation: The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the ...
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Figure 17-8. Timer/Counter Timing Diagram, with Prescaler (f Figure 17-9 Figure 17-9. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f Figure 17-10 Figure 17-10. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- 2570M–AVR–04/11 clk I/O clk ...
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Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2A, and TCCR2A might be corrupted. A safe procedure for switching ...
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SLEEP. • Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading ...
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For Timer/Counter2, the possible prescaled selections are: clk clk /128, clk T2S Setting the PSR2 bit in GTCCR resets the prescaler. This allows the user to operate with a pre- dictable prescaler. 17.11 Register Description 17.11.1 TCCR2A – Timer/Counter Control ...
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Bit 5:4 – COM2A1:0: Compare Match Output Mode A These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the I/O ...
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Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see 17-6. Table 17-6. CS22 17.11.2 TCNT2 – Timer/Counter Register ...
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Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clk written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscil- lator 1 (TOSC1) pin. ...
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TIFR2 – Timer/Counter2 Interrupt Flag Register Bit 0x17 (0x37) Read/Write Initial Value • Bit 1 – OCF2A: Output Compare Flag 2 A The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data ...
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... Double Speed (CK/2) Master SPI Mode 18.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the Atmel ATmega325/3250/645/6450 and peripheral devices or between several AVR devices. The PRSPI bit in SPI module. Figure 18-1. SPI Block Diagram Note: 2570M– ...
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The interconnection between Master and Slave CPUs with SPI is shown in tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the ...
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When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Functions” on page Table 18-1. Pin MOSI MISO SCK SS Note: 2570M–AVR–04/11 Table 18-1. For more details on automatic port ...
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The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and ...
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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 18.3 SS Pin ...
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Note that the SPI logic will be reset once the SS pin is driven high. The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the ...
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Figure 18-3. SPI Transfer Format with CPHA = 0 Figure 18-4. SPI Transfer Format with CPHA = 1 18.5 Register Description 18.5.1 SPCR – SPI Control Register Bit 0x2C (0x4C) Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt ...
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Bit 5 – DORD: Data Order When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted ...
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... WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data Register. • Bit 5:1 – Reserved Bits These bits are reserved bits in the Atmel ATmega325/3250/645/6450 and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit ...
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USART0 19.1 Features The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation ...
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Figure 19-1. USART Block Diagram Note: 2570M–AVR–04/11 (1) UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA 1. Refer to Figure 1-1 on page 2, Figure 1-2 on page 3 page 72 for USART ...
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The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units. The Clock Generation logic consists of synchronization logic for ...
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Figure 19-2. Clock Generation Logic, Block Diagram Signal description: txclk rxclk xcki operation. xcko fosc 19.3.1 Internal Clock Generation – The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The ...
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Table 19-1. Operating Mode Asynchronous Normal mode (U2Xn = 0) Asynchronous Double Speed mode (U2Xn = 1) Synchronous Master mode Note: BAUD f OSC UBRR Some examples of UBRR values for some system clock frequencies are found in (see page ...
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The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed. Figure 19-3. Synchronous Mode XCK Timing. The UCPOLn ...
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Figure 19-4. Frame Formats St ( IDLE be The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that ...
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Before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registers are changed. The TXCn Flag can be used to check that the Transmitter has completed all ...
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More advanced initialization routines can be made that include frame format as parameters, dis- able interrupts and so on. However, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization ...
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The function simply waits for the transmit buffer to be empty by checking the UDREn Flag, before loading it with new data to be transmitted. If the Data Register Empty interrupt is utilized, the interrupt routine writes the data into ...
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The Data Register Empty (UDREn) Flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has ...
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The following code example shows a simple USART receive function based on polling of the Receive Complete (RXCn) Flag. When using frames with less than eight bits the most significant bits of the data read from the UDRn will be ...
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The following code example shows a simple USART receive function that handles both nine bit characters and the status bits. Assembly Code Example USART_Receive: USART_ReceiveNoError: C Code Example unsigned int USART_Receive( void ) { } Note: The receive function example ...
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Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buf- fer. This flag is one when unread ...
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The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until ...
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Figure 19-5. Start Bit Sampling When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the ...
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Figure 19-7. Stop Bit Sampling and Next Start Bit Sampling The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 ...
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Table 19-2. # (Data+Parity Bit) Table 19-3. # (Data+Parity Bit) The recommendations of the maximum receiver baud rate error was made under the assump- tion that the Receiver and Transmitter equally divides the maximum total error. There are two possible ...
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When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit ...
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Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asyn- chronous operation can be generated by using the UBRR settings in which yield an actual baud rate differing less than ...
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Table 19-5. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% ...
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Table 19-6. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% ...
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Table 19-7. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% ...
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The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the receive buffer is accessed. Due to this behavior of the receive buffer, do not use Read-Modify- Write instructions (SBI and CBI) on this ...
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Bit 1 – U2Xn: Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using syn- chronous operation. Writing this bit to one will reduce the divisor of the ...
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Bit 2 – UCSZn2: Character Size The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits (Character SiZe frame the Receiver and Transmitter use. • Bit 1 – RXB8n: Receive Data ...
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Bit 3 – USBSn: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 19-10. USBS Bit Settings • Bit 2:1 – UCSZn1:0: Character Size The ...
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UBRRnL and UBRRnH – USART Baud Rate Registers Bit Read/Write Initial Value • Bit 15:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRH ...
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USI – Universal Serial Interface The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code space ...
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Note that when an external clock source is selected the counter counts both clock edges. In this case the counter counts the number of edges, and not the number of bits. The clock ...
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Figure 20-3. Three-wire Mode, Timing Diagram CYCLE USCK USCK The Three-wire mode timing is shown in Figure 20-3. At the top of the figure is a USCK cycle ref- erence. One bit is shifted into the USI Shift Register (USIDR) ...
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The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO and USCK pins are enabled as output in the DDRE Register. The value stored in register r16 prior to the function is ...
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SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ... SlaveSPITransfer: SlaveSPITransfer_loop: The code is size optimized using only eight instructions (+ ret). The code example assumes that the ...
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Figure 20-4. Two-wire Mode Operation, Simplified Diagram Figure 20 only the physical layer that is shown since the system operation is highly dependent of the communication scheme used. The main differences between the Master and Slave operation at ...
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The a start condition is generated by the Master by forcing the SDA low line while the SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift Register, ...
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Unit will hold the SCL low until the slave is ready to receive more data. This may reduce the actual data rate in two-wire mode. 20.3 Alternative USI Usage When the USI unit is not used for serial communication, ...
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Note that the corresponding Data Direction Register to the pin must be set to one for enabling data output from the Shift Register. 20.4.2 USISR – USI Status Register Bit (0xB9) Read/Write Initial Value The Status Register contains Interrupt Flags, ...
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USICR – USI Control Register Bit (0xB8) Read/Write Initial Value The Control Register includes interrupt enable control, wire mode setting, Clock Select setting, and clock strobe. • Bit 7 – USISIE: Start Condition Interrupt Enable Setting this bit to ...
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Table 20-1. USIWM1 Note: 2570M–AVR–04/11 Relations between USIWM1..0 and the USI Operation USIWM0 Description 0 Outputs, clock hold, and start detector disabled. Port pins operates as normal. 1 Three-wire mode. Uses DO, DI, and USCK pins. ...
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Bit 3:2 – USICS1:0: Clock Source Select These bits set the clock source for the Shift Register and counter. The data output latch ensures that the output is changed at the opposite edge of the sampling of the data ...
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Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator ...
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Analog Comparator Multiplexed Input It is possible to select any of the ADC7..0 pins to replace the negative input to the Analog Com- parator. The ADC multiplexer is used to select this input, and consequently, the ADC must be ...
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Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will ...
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Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 21-2. ACIS1 When changing the ...