PIC24FJ64GB002-I/ML Microchip Technology, PIC24FJ64GB002-I/ML Datasheet - Page 45
![IC MCU 16BIT 64KB FLASH 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC24FJ64GB002-I/ML
Manufacturer Part Number
PIC24FJ64GB002-I/ML
Description
IC MCU 16BIT 64KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.MCP73831T-2DCIOT.pdf
(28 pages)
2.PIC24FJ32GA102-ISP.pdf
(48 pages)
3.PIC24FJ32GB002-ISO.pdf
(352 pages)
4.PIC24FJ32GB002-ISO.pdf
(12 pages)
5.PIC24FJ32GB002-ISO.pdf
(342 pages)
Specifications of PIC24FJ64GB002-I/ML
Program Memory Type
FLASH
Program Memory Size
64KB (22K x 24)
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
19
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C/IrDA/SPI/UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
19
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Controller Family/series
PIC24
Ram Memory Size
8KB
Cpu Speed
32MHz
No. Of Timers
5
Embedded Interface Type
I2C, LIN, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ64GB002-I/ML
Manufacturer:
ANAREN
Quantity:
5 000
6.2
Checksums for the PIC24FJ64GA1/GB0 families are
16 bits in size. The checksum is calculated by summing
the following:
• Contents of code memory locations
• Contents of Configuration registers
TABLE 6-4:
© 2009 Microchip Technology Inc.
PIC24FJ32GA102
PIC24FJ32GA104
PIC24FJ64GA102
PIC24FJ64GA104
PIC24FJ32GB002
PIC24FJ32GB004
PIC24FJ64GB002
PIC24FJ64GB004
Legend: Item
Note:
Checksum Computation
Device
SUM[a:b] = Byte sum of locations, a to b inclusive (all 3 bytes of code memory)
CFGB
CW1 address is last location of implemented program memory; CW2 is the (last location – 2); CW3 is the
(last location – 4); CW4 is the (last location – 6).
CHECKSUM COMPUTATION
= Configuration Block (masked) byte sum of (CW1 & 0x7FFF + CW2 & 0xFFFF +
Description
CW3 & 0xFFFF + CW4 & 0xFFFF)
Read Code
Protection
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Checksum Computation
CFGB + SUM(0:0ABF7)
CFGB + SUM(0:0ABF7)
CFGB + SUM(0:0ABF7)
CFGB + SUM(0:0ABF7)
CFGB + SUM(0:057F7)
CFGB + SUM(0:057F7)
CFGB + SUM(0:057F7)
CFGB + SUM(0:057F7)
0
0
0
0
0
0
0
0
Table 6-4 describes how to calculate the checksum for
each device. All memory locations are summed, one
byte at a time, using only their native data size. More
specifically, Configuration registers are summed by
adding the lower two bytes of these locations (the
upper byte is ignored), while code memory is summed
by adding all three bytes of code memory.
PIC24FJ64GA1/GB0
Checksum
Erased
FA83h
FA83h
FA83h
FA83h
7883h
0000h
7883h
0000h
0000h
0000h
7883h
0000h
7883h
0000h
0000h
0000h
Value
Checksum with
Code Address
0xAAAAAA at
DS39934B-page 45
0x0 and Last
7685h
0000h
7685h
0000h
F885h
0000h
F885h
0000h
7685h
0000h
7685h
0000h
F885h
0000h
F885h
0000h