AT89C51RB2-RLRUL Atmel, AT89C51RB2-RLRUL Datasheet
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AT89C51RB2-RLRUL
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AT89C51RB2-RLRUL Summary of contents
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... Packages: PDIL40, PLCC44, VQFP44 Description The AT89C51RB2/RC2 is a high-performance Flash version of the 80C51 8-bit micro- controllers. It contains a 16K or 32K Bytes Flash memory block for program and data. The Flash memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. The programming voltage is internally generated from the standard VCC pin ...
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... AT89C51RB2/RC2 2 The AT89C51RB2/RC2 retains all features of the 80C52 with 256 Bytes of internal RAM, a 9-source 4-level interrupt controller and three timer/counters. In addition, the AT89C51RB2/RC2 has a Programmable Counter Array, an XRAM of 1024 Bytes, a Hardware Watchdog Timer, a Keyboard Interface, an SPI Interface, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a speed improvement mechanism (X2 mode) ...
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... XRAM + 32Kx8 or 256x8 BRG 16Kx8 C51 CORE IB-bus CPU Timer 0 Parallel I/O Ports & Ext. Bus INT Timer 1 Ctrl Port 0Port 1 Port 2 Port 3 (2) (2) (2) (2) AT89C51RB2/RC2 (1) (1) (1) (1) Boot ROM PCA Timer2 1Kx8 2Kx8 Watch Key SPI Dog Board (1) (1) (1) (1) 3 ...
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... SFR Mapping AT89C51RB2/RC2 4 The Special Function Registers (SFRs) of the AT89C51RB2/RC2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3 • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H • ...
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... SMOD1 SMOD0 - POF DPU - M0 XRS2 - - ENBOOT CKRL7 CKRL6 CKRL5 CKRL4 - WDTX2 PCAX2 SIX2 - - - ET2 - - - - PPCH PT2H - PPCL PT2L - - - - - - AT89C51RB2/RC2 RS1 RS0 GF1 GF0 PD XRS1 XRS0 EXTRAM - GF3 0 - CKRL3 CKRL2 CKRL1 T2X2 T1X2 T0X2 - - - - ET1 EX1 ET0 - - ESPI EI2C PHS PT1H PX1H ...
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... PCA Compare Capture Module 0 L CCAP1L EBh PCA Compare Capture Module 1 L CCAP2L ECh PCA Compare Capture Module 2 L CCAP3L EDh PCA Compare Capture Module 3 L CCAP4L EEh PCA Compare Capture Module 4 L AT89C51RB2/RC2 TF1 TR1 TF0 GATE1 C/T1# M11 - - - ...
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... SPR2 SPEN SSDIS MSTR SPIF WCOL SSERR MODF SPD7 SPD6 SPD5 SPD4 KBLS7 KBLS6 KBLS5 KBLS4 KBE7 KBE6 KBE5 KBE4 KBF7 KBF6 KBF5 KBF4 AT89C51RB2/RC2 TB8 RB8 TI RI TBCK RBCK SPD SRC CPOL CPHA SPR1 SPR0 - - - - SPD3 SPD2 SPD1 SPD0 3 ...
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... TMOD 88h 0000 0000 0000 0000 P0 SP 80h 0000 0111 1111 1111 0/8 1/9 1. FCON access is reserved for the Flash API and ISP software. Reserved AT89C51RB2/RC2 8 Non Bit addressable 2/A 3/B 4/C CCAP0H CCAP1H CCAPL2H XXXX XXXX XXXX CCAP0L CCAP1L CCAPL2L ...
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... PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/ P1.5/CEX2/MISO 1 P1.6/CEX3/SCK 2 P1.7/CEX4/MOSI 3 RST 4 P3.0/RxD 5 VQFP44 1.4 NIC* 6 P3.1/TxD 7 8 P3.2/INT0 P3.3/INT1 9 P3.4/T0 10 P3.5/ AT89C51RB2/RC2 P1.6/CEX3/SCK 8 9 RST 10 P3.0/RxD 11 NIC* 12 PLCC44 P3.1/TxD 13 P3.2/INT0 14 P3.3/INT1 15 P3.4/T0 16 P3.5/ P0.4/AD4 33 32 P0.5/AD5 31 P0.6/AD6 30 P0.7/AD7 29 EA ...
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... As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. Port 1 also receives the low-order address Byte during memory programming and verification. Alternate functions for AT89C51RB2/RC2 Port 1 include: 40 I/O P1.0: Input/Output I/O T2 (P1 ...
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... This pin is also the program pulse input (PROG) during Flash programming. ALE can be disabled by setting SFR’s AUXR. 0 bit. With this bit set, ALE will be inactive during internal fetches. AT89C51RB2/RC2 permits a power-on reset using SS . This pin is an output when the hardware ...
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... LCC VQFP44 1.4 PSEN AT89C51RB2/RC2 12 Type Name and Function 26 O Program Strobe Enable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory ...
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... Port Latch Data 4180E–8051–10/06 AT89C51RB2/RC2 I/O ports (P1, P2, P3) implement the quasi-bidirectional output that is common on the 80C51 and most of its derivatives. This output type can be used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic high weakly driven, allowing an external device to pull the pin low ...
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... Oscillator Registers AT89C51RB2/RC2 14 To optimize the power consumption and execution time needed for a specific task, an internal, prescaler feature has been implemented between the oscillator and the CPU and peripherals. Table 13. CKRL Register CKRL – Clock Reload Register (97h CKRL7 CKRL6 CKRL5 ...
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... CLKPER IPH 2 255 CKRL – Mode, for CKRL<>0xFF then: F OSC ---------------------------------------------- - CPU × ( CLKPER IPH 4 255 CKRL – AT89C51RB2/RC2 1 CLK PERIPH 0 CLK CPU Idle CKRL = 0xFF (Standard C51 feature) CLK PERIPH OSC /1020 (Standard Mode) /510 (X2 Mode) /2 (Standard Mode) (X2 Mode Peripheral Clock ...
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... ALE disabling • Some enhanced features are also located in the UART and the timer 2 The AT89C51RB2/RC2 core needs only 6 clock periods per machine cycle. This feature called ‘X2’ provides the following advantages: • Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. ...
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... The T0X2, T1X2, T2X2, UARTX2, PCAX2, and WDX2 bits in the CKCON0 register (Table 15) and SPIX2 bit in the CKCON1 register (see Table 16) allow a switch from standard peripheral speed (12 clock periods per peripheral clock cycle) to fast periph- eral speed (6 clock periods per peripheral clock cycle). These bits are active only in X2 mode. AT89C51RB2/RC2 X1 Mode 17 ...
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... AT89C51RB2/RC2 18 Table 15. CKCON0 Register CKCON0 - Clock Control Register (8Fh WDX2 PCAX2 Bit Bit Number Mnemonic Description 7 Reserved Watchdog Clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit 6 WDX2 has no effect). Cleared to select 6 clock periods per peripheral clock cycle. ...
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... SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). 0 SPIX2 Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Reset Value = XXXX XXX0b Not bit addressable AT89C51RB2/RC2 ...
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... Dual Data Pointer Register (DPTR) Figure 7. Use of Dual Pointer 7 AUXR1(A2H) AT89C51RB2/RC2 20 The additional data pointer can be used to speed up code execution and reduce code size. The dual DPTR structure is a way by which the chip will specify the address of an exter- nal data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1 ...
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... A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX @DPTR,A ; write the Byte to DEST 000F A3 INC DPTR ; increment DEST address 0010 70F6JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS AT89C51RB2/RC2 GF3 ...
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... AT89C51RB2/RC2 22 INC is a short (2 Bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value ...
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... Table 18. Expanded RAM Part Number XRAM Size AT89C51RB2/RC2 1024 The AT89C51RB2/RC2 has internal data memory that is mapped into four separate segments. The four segments are: 1. The Lower 128 Bytes of RAM (addresses 00h to 7Fh) are directly and indirectly addressable. 2. The Upper 128 Bytes of RAM (addresses 80h to FFh) are indirectly addressable only ...
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... AT89C51RB2/RC2 24 • Instructions that use indirect addressing access the Upper 128 Bytes of data RAM. For example: MOV @R0, # data where R0 contains 0A0h, accesses the data Byte at address 0A0h, rather than P2 (whose address is 0A0h). • The XRAM Bytes can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions ...
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... ALE Output Bit Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1 mode is used). (default) Set, ALE is active only during a MOVX or MOVC instruction is used. Reset Value = XX0X 00’HSB. XRAM’0b (see Table 65) Not bit addressable AT89C51RB2/RC2 XRS1 XRS0 EXTRAM ...
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... Auto-reload Mode AT89C51RB2/RC2 26 The Timer 2 in the AT89C51RB2/RC2 is the standard C52 Timer 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 are cascaded controlled by T2CON (Table 20) and T2MOD (Table 21) registers. Timer 2 operation is similar to Timer 0 and Timer 1C/T2 selects F operation) or external pin T2 (counter operation) as the timer clock input ...
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... To start the timer, set TR2 run control bit in T2CON register possible to use Timer baud rate generator and a clock generator simulta- neously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers. AT89C51RB2/RC2 ...
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... AT89C51RB2/RC2 28 Figure 10. Clock-Out Mode C/ FCLK PERIPH T2 T2EX TR2 T2CON TL2 2 TH (8-bit) (8-bit) RCAP2L RCAP2H (8-bit) (8-bit) Toggle Q D T2OE T2MOD EXF2 T2CON EXEN2 T2CON OVER- FLOW TIMER 2 INTERRUPT 4180E–8051–10/06 ...
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... Timer 2 Capture/Reload Bit If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to auto-reload on Timer 2 overflow. 0 CP/RL2# Cleared to auto-reload on Timer 2 overflows or negative transitions on T2EX pin if EXEN2 = 1. Set to capture on negative transitions on T2EX pin if EXEN2 = 1. Reset Value = 0000 0000b Bit addressable AT89C51RB2/RC2 TCLK EXEN2 TR2 C/T2 CP/RL2# ) ...
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... AT89C51RB2/RC2 30 Table 21. T2MOD Register T2MOD – Timer 2 Mode Control Register (C9h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...
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... CPS1 and CPS0 bits in the CMOD register (Table 22) and can be programmed to run at: peripheral clock frequency (F • 1/6 the peripheral clock frequency (F • 1/2 the • The Timer 0 overflow • The input on the ECI pin (P1.2) AT89C51RB2/RC2 ÷ CLK PERIPH ÷ CLK PERIPH External I/O Pin P1.2/ECI P1.3/CEX0 P1 ...
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... Figure 11. PCA Timer/Counter F /6 CLK PERIPH F /2 CLK PERIPH T0 OVF P1.2 Idle AT89C51RB2/RC2 32 CH CIDL WDTE CPS1 CPS0 CF CR CCF4 CCF3 CCF2 CCF1 CCF0 To PCA Modules overflow CL 16-bit up Counter CMOD ECF 0xD9 CCON 0xD8 It 4180E–8051–10/06 ...
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... ECF bit in the CMOD register is set. The CF bit can only be cleared by software. • Bits 0 through 4 are the flags for the Modules (bit 0 for Module 0, bit 1 for Module 1, etc. ) and are set by hardware when either a match or a capture occurs. These flags also can only be cleared by software. AT89C51RB2/RC2 ...
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... AT89C51RB2/RC2 34 Table 23. CCON Register CCON – PCA Counter Control Register (D8h Bit Bit Number Mnemonic Description PCA Counter Overflow Flag Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF CMOD is set. CF may be set by either hardware or software but can only be cleared by software ...
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... CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. • The last bit in the register ECOM (CCAPMn. 6) when set enables the comparator function. Table 24 shows the CCAPMn settings for the various PCA functions. AT89C51RB2/RC2 CCON 0xD8 To Interrupt Priority Decoder IEN0. 6 IEN0 ...
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... AT89C51RB2/RC2 36 Table 24. CCAPMn Registers (n = 0-4) CCAPM0 – PCA Module 0 Compare/Capture Control Register (0DAh) CCAPM1 – PCA Module 1 Compare/Capture Control Register (0DBh) CCAPM2 – PCA Module 2 Compare/Capture Control Register (0DCh) CCAPM3 – PCA Module 3 Compare/Capture Control Register (0DDh) CCAPM4 – PCA Module 4 Compare/Capture Control Register (0DEh) ...
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... CCAP4H – PCA Module 4 Compare/Capture Control Register High (0FEh Bit Bit Number Mnemonic Description PCA Module n Compare/Capture Control CCAPnH Value Reset Value = 0000 0000b Not bit addressable AT89C51RB2/RC2 TOGn PWMm ECCFn Module Function Operation 16-bit capture by a positive-edge trigger on CEXn 16-bit capture by a negative trigger ...
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... AT89C51RB2/RC2 38 Table 27. CCAPnL Registers (n = 0-4) CCAP0L – PCA Module 0 Compare/Capture Control Register Low (0EAh) CCAP1L – PCA Module 1 Compare/Capture Control Register Low (0EBh) CCAP2L – PCA Module 2 Compare/Capture Control Register Low (0ECh) CCAP3L – PCA Module 3 Compare/Capture Control Register Low (0EDh) CCAP4L – ...
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... CCAPnH). If the CCFn bit for the Module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated (see Figure 13). CR CCF4 CCF3 CCF2 CCF1 CCF0 Capture CAPPn CAPNn MATn TOGn PWMn ECCFn AT89C51RB2/RC2 CCON 0xD8 PCA IT PCA Counter/Timer CH CL CCAPnH ...
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... CCAPnH Enable 1 0 AT89C51RB2/RC2 40 The PCA Modules can be used as software timers by setting both the ECOM and MAT bits in the Modules CCAPMn register. The PCA timer will be compared to the Module's capture registers and when a match occurs, an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the Module are both set (see Figure 14) ...
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... Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register. AT89C51RB2/RC2 CCF4 CCF3 CCF2 CCF1 CCF0 Match CAPNn MATn TOGn PWMn ECCFn ...
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... Pulse Width Modulator Mode PCA Watchdog Timer AT89C51RB2/RC2 42 All of the PCA Modules can be used as PWM outputs. Figure 16 shows the PWM func- tion. The frequency of the output depends on the source for the PCA timer. All of the Modules will have the same frequency of output because they all share the PCA timer. ...
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... Modules would not be a good idea. Thus, in most appli- cations the first solution is the best option. This watchdog timer won’t generate a reset out on the reset pin. AT89C51RB2/RC2 43 ...
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... Serial I/O Port Framing Error Detection AT89C51RB2/RC2 44 The serial I/O port in the AT89C51RB2/RC2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously ...
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... SADEN1111 1100b Given0101 01XXb The following is an example of how to use given addresses to address different slaves: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b Slave C:SADDR1111 0010b SADEN1111 1101b Given1111 00X1b AT89C51RB2/RC2 Data byte Ninth bit Stop ...
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... Broadcast Address Reset Addresses AT89C51RB2/RC2 46 The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB don’t-care bit; for slaves B and C, bit 1.To commu- nicate with slave A only, the master must send an address where bit 0 is clear (e. g. ...
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... Reset Value = 0000 0000b Not bit addressable The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers. Figure 20. Baud Rate Selection TIMER1 TIMER_BRG_RX 0 TIMER2 1 RCLK INT_BRG TIMER1 TIMER_BRG_TX 0 TIMER2 1 TCLK INT_BRG AT89C51RB2/RC2 Clock RBCK Clock TBCK ...
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... Internal Baud Rate Generator (BRG) Figure 21. Internal Baud Rate AT89C51RB2/RC2 48 Table 32. Baud Rate Selection Table UART TCLK RCLK (T2CON) (T2CON) (BDRCON When the internal Baud Rate Generator is used, the Baud Rates are determined by the BRG overflow depending on the BRL reload value, the value of SPD bit (Speed Mode) in BDRCON register and the value of the SMOD1 bit in PCON register ...
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... Receive Interrupt flag Clear to acknowledge interrupt Set by hardware at the end of the 8th bit time in mode 0, see Figure 18. and Figure 19. in the other modes. Reset Value = 0000 0000b Bit addressable AT89C51RB2/RC2 REN TB8 RB8 SM1 Mode ...
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... UART Registers AT89C51RB2/RC2 50 Table 34. Example of Computed Value When X2=1, SMOD1=1, SPD=1 Baud Rates F = 16. 384 MHz OSC BRL 115200 247 57600 238 38400 229 28800 220 19200 203 9600 149 4800 43 Table 35. Example of Computed Value When X2=0, SMOD1=0, SPD=0 Baud Rates ...
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... Table 38. SBUF Register SBUF - Serial Buffer Register for UART (99h Reset Value = XXXX XXXXb Table 39. BRL Register BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah Reset Value = 0000 0000b AT89C51RB2/RC2 ...
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... AT89C51RB2/RC2 52 Table 40. T2CON Register T2CON - Timer 2 Control Register (C8h TF2 EXF2 RCLK Bit Bit Number Mnemonic Timer 2 overflow Flag 7 TF2 Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1 ...
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... Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit. AT89C51RB2/RC2 POF GF1 GF0 ...
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... AT89C51RB2/RC2 54 Table 42. BDRCON Register BDRCON - Baud Rate Control Register (9Bh Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit Reserved 6 - The value read from this bit is indeterminate. Do not set this bit Reserved 5 - The value read from this bit is indeterminate. Do not set this bit. ...
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... Individual Enable 4180E–8051–10/06 The AT89C51RB2/RC2 has a total of 9 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI inter- rupt, Keyboard interrupt and the PCA global interrupt. These interrupts are shown in Figure 22 ...
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... Registers AT89C51RB2/RC2 56 A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. Table 43. Priority Level Bit Values IPH two interrupt requests of different priority levels are received simultaneously, the request of higher-priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced ...
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... Timer 0 Overflow Interrupt Enable Bit 1 ET0 Cleared to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. External Interrupt 0 Enable Bit 0 EX0 Cleared to disable external interrupt 0. Set to enable external interrupt 0. Reset Value = 0000 0000b Bit addressable AT89C51RB2/RC2 ET1 EX1 ET0 1 0 EX0 57 ...
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... AT89C51RB2/RC2 58 Table 45. IPL0 Register IPL0 - Interrupt Priority Register (B8h PPCL PT2L Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA Interrupt Priority Bit 6 PPCL see PPCH for priority level. Timer 2 Overflow Interrupt Priority Bit ...
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... PT0H External Interrupt 0 Priority High Bit PX0H PX0L PX0H Reset Value = X000 0000b Not bit addressable AT89C51RB2/RC2 PSH PT1H PX1H Priority Level Lowest Highest Priority Level Lowest Highest Priority Level Lowest Highest Priority Level Lowest Highest Priority Level Lowest Highest Priority Level ...
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... AT89C51RB2/RC2 60 Table 47. IEN1 Register IEN1 - Interrupt Enable Register (B1h Bit Bit Number Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved SPI Interrupt Enable Bit Cleared to disable SPI interrupt. 2 ESPI Set to enable SPI interrupt Reserved Keyboard Interrupt Enable Bit 0 KBD Cleared to disable keyboard interrupt. ...
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... SPI Interrupt Priority Bit 2 SPIL see SPIH for priority level. Reserved 1 - The value read from this bit is indeterminate. Do not set this bit. Keyboard Interrupt Priority Bit 0 KBDL see KBDH for priority level. Reset Value = XXXX X000b Bit addressable AT89C51RB2/RC2 SPIL - 0 KBDL 61 ...
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... AT89C51RB2/RC2 62 Table 49. IPH1 Register IPH1 - Interrupt Priority High Register (B3h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. Reserved 5 - The value read from this bit is indeterminate. Do not set this bit. ...
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... Table 50. Interrupt Sources and Vector Addresses Number Polling Priority Interrupt Source Keyboard 9 9 AT89C51RB2/RC2 Interrupt Request Reset INT0 IE0 Timer 0 TF0 INT1 IE1 Timer 1 IF1 UART RI+TI Timer 2 TF2+EXF2 PCA CF + CCFn (n = 0-4) KBDIT SPI SPIIT Vector Address 0000h 0003h 000Bh ...
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... Interrupt Power Reduction Mode AT89C51RB2/RC2 64 The AT89C51RB2/RC2 implements a keyboard interface allowing the connection matrix keyboard based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1 and allow to exit from idle and power-down modes. ...
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... Set by hardware when the Port line 0 detects a programmed level. It generates a 0 KBF0 Keyboard interrupt request if the KBIE. 0 bit in KBIE register is set. Must be cleared by software. Reset Value = 0000 0000b This register is read only access, all flags are automatically cleared by reading the register. AT89C51RB2/RC2 KBF4 KBF3 KBF2 KBF1 ...
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... AT89C51RB2/RC2 66 Table 52. KBE Register KBE - Keyboard Input Enable Register (9Dh KBE7 KBE6 KBE5 Bit Bit Number Mnemonic Description Keyboard Line 7 Enable Bit 7 KBE7 Cleared to enable standard I/O pin. Set to enable KBF. 7 bit in KBF register to generate an interrupt request. Keyboard Line 6 Enable Bit ...
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... Cleared to enable a low level detection on Port line 1. Set to enable a high level detection on Port line 1. Keyboard Line 0 Level Selection Bit 0 KBLS0 Cleared to enable a low level detection on Port line 0. Set to enable a high level detection on Port line 0. Reset Value = 0000 0000b AT89C51RB2/RC2 KBLS4 KBLS3 KBLS2 KBLS1 ...
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... Master Input Slave Output (MISO) SPI Serial Clock (SCK) Slave Select (SS) AT89C51RB2/RC2 68 The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. Features of the SPI Module include the following: • ...
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... Table 54 gives the different clock rates selected by SPR2:SPR1:SPR0. Table 54. SPI Master Baud Rate Selection SPR2 SPR1 SPR0 AT89C51RB2/RC2 . Clock Rate Baud Rate Divisor (BD CLK PERIPH F /4 CLK PERIPH F /8 CLK PERIPH F /16 CLK PERIPH F /32 CLK PERIPH F /64 CLK PERIPH F /128 CLK PERIPH Don’t Use (2) . This 2 ...
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... Functional Description Operating Modes AT89C51RB2/RC2 70 Figure 26 shows a detailed structure of the SPI Module. Figure 26. SPI Module Block Diagram FCLK PERIPH /4 Clock /8 /16 Divider /32 /64 /128 Clock Select SPR2 SPEN SSDIS SPI Interrupt Request The Serial Peripheral Interface can be configured in one of the two modes: Master mode or Slave mode ...
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... The SPI Module should be configured as a Slave before it is enabled (SPEN set). 3. The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock speed. 4. Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = ’0’). AT89C51RB2/RC2 MISO 8-bit Shift register MOSI SCK SS ...
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... Figure 29. Data Transmission Format (CPHA = 1) SCK Cycle Number SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture Point Figure 30. CPHA/SS Timing MISO/MOSI Master SS Slave SS (CPHA = 0) Slave SS (CPHA = 1) AT89C51RB2/RC2 MSB bit6 bit5 bit4 MSB bit6 bit5 bit4 1 2 ...
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... SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt requests. When SSDIS is set, no MODF interrupt request is generated. Figure 31 gives a logical view of the above statements. AT89C51RB2/RC2 Request SPI Transmitter Interrupt request SPI Receiver/Error Interrupt Request (if SSDIS = ’0’) ...
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... Registers Serial Peripheral Control Register (SPCON) AT89C51RB2/RC2 74 Figure 31. SPI Interrupt Requests Generation SPIF SPI Transmitter CPU Interrupt Request MODF SPI Receiver/error CPU Interrupt Request SSDIS There are three registers in the Module that provide control, status and data storage functions. These registers are describes in the following paragraphs. • ...
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... Set by hardware to indicate that the SS pin is at inappropriate logic level. Reserved 3 - The value read from this bit is indeterminate. Do not set this bit Reserved 2 - The value read from this bit is indeterminate. Do not set this bit. AT89C51RB2/RC2 SPR1 SPR0 Serial Peripheral Rate CLK PERIPH 0 ...
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... Serial Peripheral DATa Register (SPDAT) AT89C51RB2/RC2 76 Bit Bit Number Mnemonic Description Reserved 1 - The value read from this bit is indeterminate. Do not set this bit. Reserved 0 - The value read from this bit is indeterminate. Do not set this bit. Reset Value = 00X0 XXXXb Not Bit addressable The Serial Peripheral Data Register (Table 58 read/write buffer for the receive data register ...
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... Table 59. WDTRST Register WDTRST - Watchdog Reset Register (0A6h Reset Value = XXXX XXXXb Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence. AT89C51RB2/RC2 , where T CLK PERIPH 7 counter has been added to extend the Time-out = 12 MHz. To manage this feature, see OSCA ...
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... WDT just before entering power-down. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the AT89C51RB2/RC2 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode. ...
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... Pull ALE low while the device is in reset (RST high) and PSEN is high. • Hold ALE low as RST is deactivated. While the AT89C51RB2/RC2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit. Table 61 shows the status of the port pins during ONCE mode. Normal operation is restored when normal reset is applied. ...
Page 80
... Cold Reset AT89C51RB2/RC2 80 Two power reduction modes are implemented in the AT89C51RB2/RC2: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addi- tion to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the X2 mode detailed in Section “X2 Feature”. ...
Page 81
... Figure 33. Figure 33. Reset Circuitry for WDT Reset-out Usage VDD + RST VDD 1K RST VSS AT89C51RB2/RC2 VDD Rise Time 10 ms 1.2 µF 3.9 µF starts from 0V to the nominal value. If the time between 2 VDD P VSS (1) 100 ms 12 µ ...
Page 82
... Prevent Flash Corruption Idle Mode Power-down Mode AT89C51RB2/RC2 82 An example of bad initialization situation may occur in an instance where the bit ENBOOT in AUXR1 register is initialized from the hardware bit BLJB upon reset. Since this bit allows mapping of the bootloader in the code area, a reset failure can be critical. ...
Page 83
... Power Down Internal Power Down External 4180E–8051–10/06 be the one following the instruction that puts the AT89C51RB2/RC2 into Power-down mode. Power-down Phase Oscillator Restart Phase Exit from Power-down by reset redefines all the SFRs, exit from Power-down by exter- nal interrupt does no affect the SFRs. ...
Page 84
... Power-off Flag AT89C51RB2/RC2 84 The Power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced still applied to the device and could be generated by an exit from Power-down. CC The Power-off flag (POF) is located in PCON register (Table 63). POF is set by hard- ware when V rises from 0 to its nominal voltage ...
Page 85
... Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), default setting, XRAM selected. ALE Output Bit Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1 mode is used). (default) Set, ALE is active only during a MOVX or MOVC instruction is used. AT89C51RB2/RC2 XRS1 XRS0 EXTRAM ...
Page 86
... EPROM programmer. The parallel programming method used by these devices is similar to that used by EPROM 87C51 but it is not identical and the commercially available programmers need to have support for the AT89C51RB2/RC2. The bootloader and the Application Programming Interface (API) routines are located in the BOOT ROM. pins of CC supply ...
Page 87
... Software registers are in a special page of the Flash memory which can be accessed through the API or with the parallel programming modes. This page, called "Extra Flash Memory", is not in the internal Flash program memory addressing space. The only hardware register of the AT89C51RB2/RC2 is called Hardware Security Byte (HSB). Table 65. Hardware Security Byte (HSB) 7 ...
Page 88
... Default Values Software Registers AT89C51RB2/RC2 88 Table 66. Program Lock Bits Program Lock Bits Security Level LB0 LB1 LB2 Protection Description program lock features enabled. MOVC instruction executed from external program memory is disabled from fetching code Bytes from internal memory sampled and latched on reset, and further parallel programming of the Flash is disabled ...
Page 89
... The two lock bits provide different levels of protection for the on-chip code and data, when programmed as shown in Table 69. AT89C51RB2/RC2 Default value Description FCh 101x 1011b 0FFh FFh 58h ATMEL D7h C51 X2, Electrically Erasable F7h AT89C51RB2/RC2 32KB FBh AT89C51RB2/RC2 16 KB AT89C51RB2/RC2 32KB, EFh Revision 0 AT89C51RB2/RC2 16 KB, FFh Revision LB1 0 LB0 89 ...
Page 90
... ISP After ISP After ISP In the AT89C51RB2/RC2, the lowest 16K or 32K of the 64 KB program memory address space is filled by internal Flash. When the EA pin is high, the processor fetches instructions from internal program Flash. Bus expansion for accessing program memory from 16K or 32K upward automatic since external instruction fetches occur automatically when the program counter exceeds 3FFFh (16K) or 7FFFh (32K) ...
Page 91
... Flash memory. Furthermore, all accesses and routines can be called from the user application. Figure 36. Diagram Context Description Access via Specific Protocol Access From User Application ISP: In-system Programming SBV: Software Boot Vector BSB: Boot Status Byte SSB: Software Security Bit HW : Hardware Byte AT89C51RB2/RC2 Bootloader Flash Memory 91 ...
Page 92
... Functional Description Figure 37. Bootloader Functional Description Exernal Host with Specific Protocol Communication AT89C51RB2/RC2 92 ISP Communication Management Flash Memory Management Flash Memory On the above diagram, the on-chip bootloader processes are: • ISP Communication Management The purpose of this process is to manage the communication and its protocol between the on-chip bootloader and a external device ...
Page 93
... Note: The BLJB test is perform by hardware to prevent any program execution. The Software Boot Vector contains the high address of custumer bootloader stored in the application. SBV = FCh (default value custumer bootloader in user Flash. SBV Note: The costumer bootloader is called by JMP [SBV]00h instruction. AT89C51RB2/RC2 93 ...
Page 94
... Boot Process Figure 39. Bootloader process PC = 0000h USER APPLICATION AT89C51RB2/RC2 94 RESET If BLJB = 0 then ENBOOT bit (AUXR1) is set else ENBOOT bit (AUXR1) is cleared Yes (PSEN = and ALE = 1 or not connected) FCON = 00h Hardware Condition? FCON = F0h BLJB = 1 BLJB!= 0 ENBOOT = 0 ? BLJB = 0 ENBOOT = 1 F800h yes = hardware boot ...
Page 95
... ASCII hexadecimal digits to one Byte of binary, and including the Reclen field to and including the last Byte of the Data/Info field. Therefore, the sum of all the ASCII pairs in a record after converting to binary, from the Reclen field to and including the Checksum field, is zero. AT89C51RB2/RC2 Record Type Data or Info 2 bytes ...
Page 96
... Functional Description Software Security Bits (SSB) AT89C51RB2/RC2 96 The SSB protects any Flash access from ISP command. The command "Program Software Security bit" can only write a higher priority level. There are three levels of security: • level 0: NO_SECURITY (FFh) This is the default level. ...
Page 97
... Atmel the web site. The host initializes the communication by sending a ’U’ character to help the bootloader to compute the baudrate (autobaud). Figure 40. Initialization Host Init Communication If (not received "U") Else Communication Opened AT89C51RB2/RC2 Bootloader "U" Performs Autobaud Sends Back ‘U’ Character "U" 97 ...
Page 98
... This is accomplished by measuring the bit-time of a single bit in a received character. This information is then used to pro- gram the baud rate in terms of timer counts based on the oscillator frequency. The ISP itia AT89C51RB2/RC2 to establish the baud rate. Table 72 shows the autobaud capability. 2 2.4576 3 3 ...
Page 99
... Config Byte Programming Data Frame • Baud Rate Frame Write Command ’X’ & CR & LF ’P’ & CR & LF ’.’ & CR & LF AT89C51RB2/RC2 Bootloader If (not received ":") Else Sends echo and start reception Gets frame, and sends back ec for each received Byte ...
Page 100
... Example AT89C51RB2/RC2 100 Programming Data (write 55h at address 0010h in the Flash) HOST : 01 0010 BOOTLOADER : 01 0010 Programming Atmel function (write SSB to level 2) HOST : 02 0000 BOOTLOADER : 02 0000 F5 Writing Frame (write BSB to 55h) HOST : 03 0000 BOOTLOADER : 03 0000 4180E–8051–10/06 ...
Page 101
... BOOTLOADER : 05 0000 04 0000 7FFF 01 78 xxxx CR LF Blank Check with checksum error HOST : 05 0000 04 0000 7FFF 01 70 BOOTLOADER : 05 0000 04 0000 7FFF AT89C51RB2/RC2 Bootloader Wait Blank Check Command Checksum error Send Checksum error Flash blank Send COMMAND_OK Send first Address ...
Page 102
... COMMAND ABORTED Wait Display Data All data read COMMAND FINISHED Note: The maximum size of block is 400h. To read more than 400h Bytes, the Host must send a new command. AT89C51RB2/RC2 102 Display Command ’X’ & CR & LF Send Checksum Error ’L’ & CR & LF ...
Page 103
... Read function (read SBV) HOST : 02 0000 BOOTLOADER : 02 0000 Value . CR LF Atmel Read function (read Bootloader version) HOST : 02 0000 BOOTLOADER : 02 0000 Value . CR LF AT89C51RB2/RC2 (16 data) (16 data data) Bootloader Wait Read Command Checksum error Send Checksum error RD_WR_SECURITY Send Security error Read Value ...
Page 104
... ISP Commands Summary AT89C51RB2/RC2 104 Table 73. ISP Commands Summary Command Command Name Data[0] 00h Program Data 03h Write Function Data[0:1] = start address Data [2:3] = end address 04h Display Function Data[4] = 00h -> Display data Data[4] = 01h -> Blank check 05h Read Function Data[1] Command Effect Program Nb Data Byte ...
Page 105
... XXh Address of Address in the first byte XRAM of the to program in first data to the Flash program memory AT89C51RB2/RC2 Returned Value Command Effect Read Manufacturer identifier Id ACC = Device Id 1 Read Device identifier 1 ACC = Device Id 2 Read Device identifier 2 ACC = Device Id 3 Read Device identifier 3 ...
Page 106
... FUSE 00h or 01h READ HSB 0Bh XXh READ BOOT ID1 0Eh XXh READ BOOT ID2 0Eh XXh READ BOOT VERSION 0Fh XXh AT89C51RB2/RC2 106 DPTR0 DPTR1 Returned Value 0008h XXh none 0004h XXh none XXXXh XXh ACC = HSB DPL = 00h ...
Page 107
... 1 AT89C51RB2/RC2 Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Expo- sure to absolute maximum rating conditions may affect device reliability ...
Page 108
... V OL than the listed test conditions. 7. For other values, please contact your sales office. 8. Icc Flash Write operation current while an on-chip flash page write is on going. 9. Flash Retention is guaranteed with the same formula for V AT89C51RB2/RC2 108 Min Typ V - 0.3 ...
Page 109
... Min Typ -0.5 0 0 (6) ( 200 10 0.4 x Frequency (MHz would be slightly higher if a crystal oscillator used (see Figure RST = V (see Figure 47 must be externally limited as follows: OL AT89C51RB2/RC2 Max Unit 0. μA -50 ±10 μA μA -650 (5) 250 kΩ μ ...
Page 110
... V OL than the listed test conditions. 7. For other values, please contact your sales office. 8. Icc Flash Write operation current while an on-chip flash page write is on going. AT89C51RB2/RC2 110 may exceed the related specification. Pins are not guaranteed to sink current greater OL Figure 46. I ...
Page 111
... Address Hold after ALE LLAX T ALE to Valid Instruction In LLIV T ALE to PSEN LLPL T PSEN Pulse Width PLPH T PSEN to Valid Instruction In PLIV T Input Instruction Hold after PSEN PXIX T Input Instruction Float after PSEN PXIZ T Address to Valid Instruction In AVIV T PSEN Low to Address Float PLAZ AT89C51RB2/RC2 111 ...
Page 112
... AT89C51RB2/RC2 112 Table 76. AC Parameters for a Fix Clock Symbol -M Min LHLL T 5 AVLL T 5 LLAX T LLIV T 5 LLPL T 50 PLPH T PLIV T 0 PXIX T PXIZ T AVIV T PLAZ Table 77. AC Parameters for a Variable Clock Standard Symbol Type Clock T Min LHLL T Min AVLL T Min ...
Page 113
... ALE to Valid Data In LLDV T Address to Valid Data In AVDV T ALE LLWL T Address AVWL T Data Valid to WR Transition QVWX T Data set- High QVWH T Data Hold After WR WHQX T RD Low to Address Float RLAZ High to ALE high WHLH AT89C51RB2/RC2 CLCL T PXAV T PXIZ A0-A7 INSTR IN ADDRESS A8-A15 113 ...
Page 114
... AT89C51RB2/RC2 114 Table 79. AC Parameters for a Fix Clock -M Symbol Min T 125 RLRH T 125 WLWH T RLDV T 0 RHDX T RHDZ T LLDV T AVDV T 45 LLWL T 70 AVWL T 5 QVWX T 155 QVWH T 10 WHQX T 0 RLAZ T 5 WHLH -L Max Min Max 125 125 155 155 ...
Page 115
... Max 1 LLWL T Min AVWL T Min 0 QVWX T Min 3 QVWH T Min 0 WHQX T Max x x RLAZ T Min 0 WHLH T Max 0 WHLH T LLWL T QVWX T LLAX A0-A7 T AVWL ADDRESS A8-A15 OR SFR P2 AT89C51RB2/RC2 X Parameter for - X Parameter for - M Range L Range WHLH T WLWH T T WHQX QVWH DATA OUT Units ns ns ...
Page 116
... External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Serial Port Timing - Shift Register Mode AT89C51RB2/RC2 116 T LLDV T LLWL T AVDV T LLAX A0-A7 T RLAZ T AVWL ADDRESS A8-A15 OR SFR P2 Table 80. Symbol Description Symbol Parameter T Serial port clock cycle time XLXL ...
Page 117
... OL For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V ≥ ± 20mA. occurs Valid in normal clock mode mode XTAL2 must be changed to XTAL2/2. AT89C51RB2/RC2 SET TI VALID VALID ...
Page 118
... This propagation delay is dependent on variables such as temperature and pin loading. Propaga- tion also varies from output to output and component. Typically though (T delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. AT89C51RB2/RC2 118 STATE5 STATE6 ...
Page 119
... Memory Size AT89C51RB2-3CSIM AT89C51RB2-SLSCM AT89C51RB2-SLSIM AT89C51RB2-RLTCM 16 KBytes AT89C51RB2-RLTIM AT89C51RB2-SLSIL AT89C51RB2-RLTIL AT89C51RC2-3CSCM AT89C51RC2-3CSIM AT89C51RC2-SLSCM AT89C51RC2-SLSIM 32 KBytes AT89C51RC2-RLTCM AT89C51RC2-RLTIM AT89C51RC2-SLSIL AT89C51RC2-RLTIL AT89C51RB2-3CSUM AT89C51RB2-SLSUM AT89C51RB2-RLTUM 16 KBytes AT89C51RB2-SLSUL AT89C51RB2-RLTUL AT89C51RB2-RLTUM AT89C51RC2-3CSUM AT89C51RC2-SLSUM AT89C51RC2-RLTUM 32 KBytes AT89C51RC2-SLSUL AT89C51RC2-RLTUL 4180E–8051–10/06 Supply Voltage Temperature Range 5V Industrial 5V Commercial 5V Industrial ...
Page 120
... Package Information PDIL40 AT89C51RB2/RC2 120 4180E–8051–10/06 ...
Page 121
... VQFP44 4180E–8051–10/06 AT89C51RB2/RC2 121 ...
Page 122
... PLC44 AT89C51RB2/RC2 122 4180E–8051–10/06 ...
Page 123
... Changed the endurance of Flash to 100, 000 Write/Erase cycles. 2. Added note on Flash retention formula for V Standard Voltage”, page 107. 1. Max frequency update for 4.5 to 5.5V range MHz (internal code execution). 1. Added Green product ordering information. Page 119. 1. Correction to PDIL40 figure on page 9. AT89C51RB2/RC2 , in Section “DC Parameters for IH1 123 ...
Page 124
Table of Contents Features ................................................................................................. 1 Description ............................................................................................ 1 Block Diagram ....................................................................................... 3 SFR Mapping ......................................................................................... 4 Pin Configurations ................................................................................ 9 Port Types ........................................................................................... 13 Oscillator ............................................................................................. 14 Enhanced Features ............................................................................. 16 Dual Data Pointer Register (DPTR) ................................................... 20 Expanded ...
Page 125
Registers............................................................................................................. 47 Baud Rate Selection for UART for Mode 1 and 3............................................... 47 UART Registers.................................................................................................. 50 Interrupt System ................................................................................. 55 Registers............................................................................................................. 56 Interrupt Sources and Vector Addresses............................................................ 63 Keyboard Interface ............................................................................. 64 Registers............................................................................................................. 65 Serial Port Interface (SPI) ................................................................... ...
Page 126
DC Parameters for Standard Voltage ............................................................... 107 DC Parameters for Low Voltage ....................................................................... 109 AC Parameters ................................................................................................. 111 Ordering Information ........................................................................ 119 Package Information ........................................................................ 120 PDIL40.............................................................................................................. 120 VQFP44 ............................................................................................................ 121 PLC44............................................................................................................... 122 Datasheet Change Log ..................................................................... 123 Changes ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...