DSPIC33FJ64MC510T-I/PF Microchip Technology, DSPIC33FJ64MC510T-I/PF Datasheet - Page 212
![IC DSPIC MCU/DSP 64K 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
DSPIC33FJ64MC510T-I/PF
Manufacturer Part Number
DSPIC33FJ64MC510T-I/PF
Description
IC DSPIC MCU/DSP 64K 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.MA330013.pdf
(370 pages)
2.PIC24HJ12GP201-ISO.pdf
(84 pages)
3.DSPIC33FJ64MC506-IPT.pdf
(340 pages)
4.DSPIC33FJ64MC506-IPT.pdf
(30 pages)
Specifications of DSPIC33FJ64MC510T-I/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
For Use With
MA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164323 - MODULE SKT FOR 100TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ64MC510T-I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
- MA330013 PDF datasheet
- PIC24HJ12GP201-ISO PDF datasheet #2
- DSPIC33FJ64MC506-IPT PDF datasheet #3
- DSPIC33FJ64MC506-IPT PDF datasheet #4
- Current page: 212 of 340
- Download datasheet (5Mb)
dsPIC33FJXXXMCX06/X08/X10
REGISTER 20-1:
DS70287C-page 210
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5
UARTEN
R/W-0 HC
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F Family Reference Manual” for information on
WAKE
R/W-0
2: This feature is only available for the 16x BRG mode (BRGH = 0).
(1)
enabling the UART module for receive or transmit operation.
UARTEN: UARTx Enable bit
1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption
Unimplemented: Read as ‘0’
USIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
IREN: IrDA
1 = IrDA
0 = IrDA
RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin in Simplex mode
0 = UxRTS pin in Flow Control mode
Unimplemented: Read as ‘0’
UEN<1:0>: UARTx Enable bits
11 = UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin controlled by port latches
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by port latches
00 = UxTX and UxRX pins are enabled and used; and UxRTS/BCLK pins controlled by
WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit
1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge; bit cleared
0 = No wake-up enabled
LPBACK: UARTx Loopback Mode Select bit
1 = Enable Loopback mode
0 = Loopback mode is disabled
ABAUD: Auto-Baud Enable bit
1 = Enable baud rate measurement on the next character – requires reception of a Sync field (0x55)
0 = Baud rate measurement disabled or completed
LPBACK
R/W-0
minimal
in hardware on following rising edge
before other data; cleared in hardware upon completion
U-0
port latches
—
UxMODE: UART
®
®
encoder and decoder enabled
encoder and decoder disabled
®
Encoder and Decoder Enable bit
HC = Hardware cleared
W = Writable bit
‘1’ = Bit is set
R/W-0 HC
ABAUD
USIDL
R/W-0
x
MODE REGISTER
(1)
URXINV
IREN
R/W-0
R/W-0
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
RTSMD
(2)
BRGH
R/W-0
R/W-0
R/W-0
U-0
—
PDSEL<1:0>
© 2009 Microchip Technology Inc.
x = Bit is unknown
R/W-0
R/W-0
UEN<1:0>
STSEL
R/W-0
R/W-0
bit 8
bit 0
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