PIC16LC62A-04I/SS Microchip Technology, PIC16LC62A-04I/SS Datasheet - Page 139
![IC MCU OTP 2KX14 PWM 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC16LC62A-04I/SS
Manufacturer Part Number
PIC16LC62A-04I/SS
Description
IC MCU OTP 2KX14 PWM 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheet
1.PIC16LC62A-04SP.pdf
(337 pages)
Specifications of PIC16LC62A-04I/SS
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Processor Series
PIC16LC
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
I2C, SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
22
Number Of Timers
3 bit
Operating Supply Voltage
2.5 V to 6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000, DM163022
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
- Current page: 139 of 337
- Download datasheet (3Mb)
13.6
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt i.e., W register and STATUS
register. This will have to be implemented in software.
Example 13-1 stores and restores the STATUS and W
registers. Example 13-2 stores and restores the
STATUS, W, and PCLATH registers (Devices with
paged program memory). For all PIC16C6X devices
with greater than 1K of program memory (all devices
except PIC16C61), the register, W_TEMP, must be
EXAMPLE 13-1: SAVING STATUS AND W REGISTERS IN RAM (PIC16C61)
EXAMPLE 13-2: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
1997 Microchip Technology Inc.
MOVWF
SWAPF
MOVWF
:
:(ISR)
:
SWAPF
MOVWF
SWAPF
SWAPF
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
CLRF
BCF
MOVF
MOVWF
:(ISR)
:
MOVF
MOVWF
SWAPF
MOVWF
SWAPF
SWAPF
Context Saving During Interrupts
W_TEMP
STATUS,W
STATUS_TEMP
STATUS_TEMP,W
STATUS
W_TEMP,F
W_TEMP,W
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
STATUS, IRP
FSR, W
FSR_TEMP
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
STATUS
W_TEMP,F
W_TEMP,W
(ALL OTHER PIC16C6X DEVICES)
;Copy W to TEMP register, could be bank one or zero
;Swap status to be saved into W
;Save status to bank zero STATUS_TEMP register
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
;Copy W to TEMP register, could be bank one or zero
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
;Only required if using pages 1, 2 and/or 3
;Save PCLATH into W
;Page zero, regardless of current page
;Return to Bank 0
;Copy FSR to W
;Copy FSR from W to FSR_TEMP
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
defined in
offset from the bank base address (i.e., if W_TEMP is
defined at 0x20 in bank 0, it must also be defined at
0xA0 in bank 1, 0x120 in bank 2, and 0x1A0 in bank 3).
The examples:
a)
b)
c)
d)
e)
f)
g)
Stores the W register
Stores the STATUS register in bank 0
Stores PCLATH
Executes ISR code
Restores PCLATH
Restores STATUS register (and bank select bit)
Restores W register
all
banks and must be defined at the same
PIC16C6X
DS30234D-page 139
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