PIC18F67K90-I/PTRSL Microchip Technology, PIC18F67K90-I/PTRSL Datasheet
PIC18F67K90-I/PTRSL
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PIC18F67K90-I/PTRSL Summary of contents
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... Microcontrollers with LCD Driver and 2010 Microchip Technology Inc. PIC18F87K90 Family Data Sheet 64/80-Pin, High-Performance nanoWatt XLP Technology Preliminary DS39957B ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Low-Power Resistor Bias Network for LCD Flash SRAM Program Data EEPROM Device Memory Memory (Bytes) (Bytes) PIC18F65K90 32K 2K PIC18F66K90 64K 4K PIC18F67K90 128K 4K PIC18F85K90 32K 2K PIC18F86K90 64K 4K PIC18F87K90 128K 4K 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Peripheral Highlights: • Ten or eight CCP/ECCP modules: - Seven Capture/Compare/PWM (CCP) modules ...
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... In-Circuit Debug via Two Pins • Programmable: - BOR - LVD • Two Enhanced Addressable USART modules: - LIN/J2602 support - Auto-Baud Detect (ABD) • 12-Bit A/D Converter with Channels: - Auto-acquisition and Sleep operation - Differential Input mode of operation Preliminary 2010 Microchip Technology Inc. ...
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... REF RF4/AN9/SEG22/C2INA RF3/AN8/SEG21/C2INB/CTMUI RF2/AN7/C1OUT/SEG20 Note 1: The ECCP2 pin placement depends on the CCP2MX Configuration bit setting. 2: Not available in the PIC18F65K90 and PIC18F85K90. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY PIC18F65K90 6 7 PIC18F66K90 8 PIC18F67K90 CAP Preliminary 50 49 RB0/INT0/SEG30/FLTO 48 RB1/INT1/SEG8 47 RB2/INT2/SEG9/CTED1 46 45 RB3/INT3/SEG10/CTED2/P2A ...
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... RJ3/SEG35 RJ3/SEG35 58 RB0/INT0/SEG30/FLT0 RB0/INT0/SEG30/FLT0 RB1/INT1/SEG8 RB1/INT1/SEG8 57 56 RB2/INT2/SEG9/CTED1 RB2/INT2/SEG9/CTED1 55 RB3/INT3/SEG10/CTED2/P2A 54 RB4/KBI0/SEG11 RB4/KBI0/SEG11 53 RB5/KBI1/SEG29/T3CKI/T1G 52 RB6/KBI2/PGC RB6/KBI2/PGC OSC2/CLKO/RA6 OSC2/CLKO/RA6 49 OSC1/CLKI/RA7 OSC1/CLKI/RA7 RB7/KBI3/PGD RB7/KBI3/PGD RC5/SDO1/SEG12 RC5/SDO1/SEG12 46 45 RC4/SDI1/SDA1/SEG16 RC4/SDI1/SDA1/SEG16 RC3/SCK1/SCL1/SEG17 RC3/SCK1/SCL1/SEG17 44 43 RC2/ECCP1/P1A/SEG13 RC2/ECCP1/P1A/SEG13 RJ7/SEG36 RJ7/SEG36 42 41 RJ6/SEG37 RJ6/SEG37 2010 Microchip Technology Inc. ...
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... Appendix A: Revision History............................................................................................................................................................. 549 Appendix B: Migration From PIC18F85J90 and PIC18F87J90 to PIC18F87K90 .............................................................................. 549 Index ................................................................................................................................................................................................. 551 The Microchip Web Site ..................................................................................................................................................................... 563 Customer Change Notification Service .............................................................................................................................................. 563 Customer Support .............................................................................................................................................................................. 563 Reader Response .............................................................................................................................................................................. 564 Product Identification System ............................................................................................................................................................ 565 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Preliminary DS39957B-page 7 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39957B-page 8 Preliminary 2010 Microchip Technology Inc. ...
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... PIC18F65K90 • PIC18F85K90 • PIC18F66K90 • PIC18F86K90 • PIC18F67K90 • PIC18F87K90 This family combines the traditional advantages of all PIC18 microcontrollers – namely, high computational performance and a rich feature set – with a versatile on-chip LCD driver, while maintaining an extremely competitive price point ...
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... Flash Program Memory – - PIC18FX5K90 (PIC18F65K90 and PIC18F85K90) – 32 Kbytes - PIC18FX6K90 (PIC18F66K90 and PIC18F86K90) – 64 Kbytes - PIC18FX7K90 (PIC18F67K90 and PIC18F87K90) – 128 Kbytes • Data RAM - All devices except PIC18FX5K90 – 4 Kbytes - PIC18FX5K90 – 2 Kbytes • I/O Ports - PIC18F6XK90 (64-pin devices) – Seven bidirectional ports - PIC18F8XK90 (80-pin devices) – ...
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... SEGs x 4 COMs Yes Yes Two MSSP and two Enhanced USART (EUSART) 24 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) 75 Instructions, 83 with Extended Instruction Set Enabled 80-Pin TQFP Preliminary PIC18F67K90 128K 65,536 PIC18F87K90 128K 65,536 DS39957B-page 11 ...
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... Timer LVD MCLR SS Timer ADC CTMU (3) (3) /12 3/5/7 12-Bit RTCC MSSP1/2 EUSART2 Preliminary PORTA (1,2) RA0:RA7 12 PORTB (1) RB0:RB7 4 Access Bank 12 PORTC (1) RC0:RC7 PORTD (1) RD0:RD7 8 PRODL PORTE (1) RE0:RE7 PORTF 8 (1) RF1:RF7 8 PORTG (1) RG0:RG5 Comparator 1/2/3 LCD Driver 2010 Microchip Technology Inc. ...
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... See Table 1-3 for I/O port pin descriptions. 2: RA6 and RA7 are only available as digital I/O in select oscillator modes. See Section 3.0 “Oscillator Configurations” for more information. 3: Unimplemented on the PIC18F85K90. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Data Bus<8> Data Latch 8 8 ...
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... In certain oscillator modes, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD 2010 Microchip Technology Inc. ...
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... Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Pin Buffer Type Type PORTA is a bidirectional I/O port. ...
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... In-Circuit Debugger and ICSP™ programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD 2010 Microchip Technology Inc. ...
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... Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port. ...
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... Synchronous serial clock Synchronous serial clock for I I/O ST Digital I/O. O Analog SEG7 output for LCD. I TTL SPI slave select input. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description 2 C mode 2010 Microchip Technology Inc. ...
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... Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Pin Buffer Type Type PORTE is a bidirectional I/O port. ...
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... SEG24 output for LCD I Analog Comparator 1 Input A. I/O ST Digital I/O. O AnalogT Analog Input SPI1 slave select input. O Analog SEG25 output for LCD. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD 2010 Microchip Technology Inc. ...
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... Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Pin Buffer Type Type PORTG is a bidirectional I/O port. ...
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... In certain oscillator modes, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD Description ) DD 2010 Microchip Technology Inc. ...
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... Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 4: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Pin Buffer Type Type PORTA is a bidirectional I/O port ...
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... SEG11 output for LCD. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. O Analog SEG29 output for LCD Timer3 clock input Timer1 external clock gate input. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD 2010 Microchip Technology Inc. ...
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... Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 4: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Pin Buffer Type Type ...
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... SEG27 output for LCD. I/O ST Digital I/ EUSART asynchronous receive. I/O ST EUSART synchronous data (see related TX1/CK1). O Analog SEG28 output for LCD. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description 2 C™ mode 2010 Microchip Technology Inc. ...
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... Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 4: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Pin Buffer Type Type PORTD is a bidirectional I/O port ...
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... Capture 6 input/Compare 6 output/PWM6 output. I/O ST Digital I/O. I/O ST Capture 2 input/Compare 2 output/PWM2 output. O — ECCP2 PWM Output A. O Analog SEG31 output for LCD. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD 2010 Microchip Technology Inc. ...
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... Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 4: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Pin Buffer Type Type PORTF is a bidirectional I/O port ...
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... I/O ST Capture 5 input/Compare 5 output/PWM5 output. I Analog Analog Input 16. O — ECCP1 PWM Output D. I Analog Comparator 3 Input C. See the MCLR/RG5 pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD 2010 Microchip Technology Inc. ...
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... Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 4: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Pin Buffer Type Type PORTH is a bidirectional I/O port ...
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... I/O ST Digital I/O. O Analog SEG43 output for LCD. I/O ST Capture 6 input/Compare 6 output/PWM6 output. O — ECCP1 PWM Output B. I Analog Analog Input 15. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD 2010 Microchip Technology Inc. ...
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... Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 4: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Pin Buffer Type Type PORTJ is a bidirectional I/O port ...
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... PIC18F87K90 FAMILY NOTES: DS39957B-page 34 Preliminary 2010 Microchip Technology Inc. ...
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... REF reference for analog modules is implemented Note: The AV and AV pins must always connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY FIGURE 2- MCLR C1 V (2) C6 ...
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... The DD may be beneficial. A typical ) and fast signal transitions must IL is replaced for normal run-time EXAMPLE OF MCLR PIN CONNECTIONS R1 R2 MCLR PIC18FXXKXX JP C1 and V specifications are met and V specifications are met. IL 2010 Microchip Technology Inc. ...
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... These devices also do not have the ENVREG pin. The 10F capacitor is still required on the V /V pin. CAP DDCORE For details on all members of the PIC18F87K90 family, see Section 28.3 “On-Chip Voltage Regulator”. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY FIGURE 2-3: 10 enables DD 1 0.1 pin to DDCORE 0 ...
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... Copper Pour (tied to ground) OSCO GND Devices” OSCI DEVICE PINS Preliminary SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Primary Oscillator Crystal DEVICE PINS OSC1 ` OSC2 GND ` T1OSO T1OS Oscillator: C2 Top Layer Copper Pour (tied to ground) C2 Oscillator Crystal C1 2010 Microchip Technology Inc. ...
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... When the RA6 and RA7 pins are not used for an oscil- lator function or CLKOUT function, they are available as general purpose I/Os. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY To optimize power consumption when using EC/HS/ XT/LP/RC as the primary oscillator, the frequency input ...
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... INTSRC MFIOSEL Preliminary OSC<3:0> Setting 1101 1100 1011 1010 0101 0100 0011 0010 0001 0000 011x 100x (and OSCCON, OSCCON2) Peripherals CPU IDLEN Clock Control SCS<1:0> FOSC<3:0> IRCF<2:0> 2010 Microchip Technology Inc. ...
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... Modifying these bits will cause an immediate clock source switch. 5: INTSRC = OSCTUNE<7> and MFIOSEL = OSCCON2<0>. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY The OSCTUNE register (Register 3-3) controls the tuning and operation of the internal oscillator block. It also implements the PLLEN bit which controls the operation of the Phase Locked Loop (PLL) (see Section 3.5.2 “ ...
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... MF-INTOSC is used in place of HF-INTOSC frequencies of 500 kHz, 250 kHz and 31.25 kHz 0 = MF-INTOSC is not used DS39957B-page 42 (1) (CONTINUED) (4) U-0 R/W-0 U-0 — SOSCGO — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary 2010 Microchip Technology Inc. R-x R/W-0 MFIOFS MFIOSEL bit Bit is unknown ...
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... The secondary oscillators are external clock sources that are not connected to the OSC1 or OSC2 pin. These sources may continue to operate, even after the controller is placed in a power-managed mode. PIC18F87K90 family devices offer the SOSC 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-0 R/W-0 ...
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... The oscillator design requires the use of a crystal rated for parallel resonant operation. Note: Use of a crystal rated for series resonant operation may give a frequency out of the crystal manufacturer’s specifications. Preliminary Figure 3-2 shows the pin 2010 Microchip Technology Inc. ...
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... Table 3-2 for oscillator-specific information. Also see the notes following this table information. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Note 1: Higher capacitance increases the stability of oscillator but also increases the start-up time. 2: Since each resonator/crystal has its own OSC2 characteristics, the user should consult ...
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... HF-INTOSC mode only if the input frequency is in the range of 4 MHz-16 MHz. Preliminary EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI PIC18F87K90 F /4 OSC2/CLKO OSC EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 PIC18F87K90 (HS Mode) OSC2 Open HSPLL and ECPLL Modes 2010 Microchip Technology Inc. ...
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... MHz. If HF-INTOSC is used with the PLL, the input frequency to the PLL should be 4 MHz to 16 MHz (IRCF<2:0> = 111, 110 or 101). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY For MF-INTOSC mode to provide a frequency range of 500 kHz to 31 kHz, INTSRC = 1 and MFIOSEL = 1. ...
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... To compensate, decrement the OSCTUNE register. If the measured time is much less than the calculated time, the internal oscillator block is running too slow. To compensate, increment the OSCTUNE or tempera- DD register. Preliminary 2010 Microchip Technology Inc. ...
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... Note 1: For ROSEL (REFOCON<4>), the primary oscillator is only available when configured as default via the FOSC settings (regardless of whether the device is in Sleep mode). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY The ROSSLP and ROSEL bits (REFOCON<5:4>) con- trol the availability of the reference output during Sleep mode ...
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... There is a delay of interval, T Table 31-10), following POR, while the controller becomes ready to execute instructions. OSC1 Pin At logic low (clock/4 output) Feedback inverter disabled at quiescent voltage level I/O pin, RA6, direction controlled by TRISA<7> Preliminary (parameter 38, CSD OSC2 Pin 2010 Microchip Technology Inc. ...
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... IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC (HF-INTOSC and MG-INTOSC) and INTOSC postscaler, as well as the LF-INTISC source. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY The IDLEN bit (OSCCON<7>) controls CPU clocking, while the SCS<1:0> bits (OSCCON<1:0>) select the clock source ...
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... Figure 4-2). When the clock switch is complete, the SOSCRUN bit is cleared, the OSTS bit is set and the . Improper DD primary clock is providing the clock. The IDLEN and / DD SCS bits are not affected by the wake-up and the SOSC oscillator continues to run. Preliminary 2010 Microchip Technology Inc. ...
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... HF-INTOSC) – there are no distinguishable differences between the PRI_RUN and RC_RUN modes during execution. Entering or exiting RC_RUN mode, however, causes a clock switch delay. Therefore, if the primary clock source is the internal oscillator block, using RC_RUN mode is not recommended. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY n-1 ...
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... OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch. The LF-INTOSC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. Preliminary 2010 Microchip Technology Inc. ...
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... PLL Clock Output CPU Clock Peripheral Clock Program Counter SCS<1:0> bits Changed Note1 1024 (approx). These intervals are not shown to scale. OST OSC PLL 2: Clock transition typically occurs within 2-4 T 2010 Microchip Technology Inc. PIC18F87K90 FAMILY n-1 n (1) Clock Transition OSC ...
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... IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or Sleep mode, a WDT time- out will result in a WDT wake-up to the Run mode currently specified by the SCS<1:0> bits (1) T PLL OSTS bit Set Preliminary CSD 2010 Microchip Technology Inc. ...
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... OSC1 CPU Clock Peripheral Clock Program Counter Wake Event 2010 Microchip Technology Inc. PIC18F87K90 FAMILY 4.4.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the SOSC oscillator. This mode is entered from SEC_RUN by set- ting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set the IDLEN bit first, then set the SCS< ...
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... PMD bit. There are four PMD registers in PIC18F87K90 family devices: PMD0, PMD1, PMD2 and PMD3. These registers have bits associated with each module for disabling or enabling a particular peripheral. Preliminary 2010 Microchip Technology Inc. eliminating their power ...
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... PMD is disabled for CCP4 bit 0 TMR12MD: TMR12MD Disable bit 1 = PMD is enabled and all TMR12MD clock sources are disabled 0 = PMD is disabled and TMR12MD is enabled Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K90). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-0 R/W-0 CCP7MD CCP6MD CCP5MD U = Unimplemented bit, read as ‘ ...
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... PMD is disabled for Comparator 1 Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K90). DS39957B-page 60 R/W-0 R/W-0 R/W-0 (1) TMR6MD TMR5MD CMP3MD U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) Preliminary R/W-0 R/W-0 CMP2MD CMP1MD bit Bit is unknown 2010 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ Note 1: RTCCMD can only be set to ‘1’ after an EECON2 unlock sequence; refer to Section 17.0 “Real-Time Clock and Calendar (RTCC)” for the unlock sequence (see Example 17-1). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-0 R/W-0 ...
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... PMD is enabled for Analog/Digital Converter, disabling all of its clock sources 0 = PMD is disabled for Analog/Digital Converter DS39957B-page 62 R/W-0 R/W-0 R/W-0 UART2MD UART1MD SSP2MD U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SSP1MD ADCMD bit Bit is unknown 2010 Microchip Technology Inc. ...
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... WDT timer and postscaler, loses the currently selected clock source (if the Fail-Safe Clock Monitor is enabled) and modifies the IRCF bits in the OSCCON register (if the internal oscillator block is the device clock source). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY 4.6.3 EXIT BY RESET ...
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... The peripheral can also be configured as a simple programmable temperature sensor. Note: For more information, see AN 879, “Using the Microchip Ultra Low-Power Wake-up Module” (DS00879). Preliminary ULTRA LOW-POWER WAKE-UP INITIALIZATION Low-Voltage Detect (LVD) or 2010 Microchip Technology Inc. ...
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... OST (parameter F12, Table 31-7 also designated Execution continues during T 5: The clock source is dependent upon the settings of the SCS (OSCCON<1:0>), IRCF (OSCCON<6:4>) and FOSC (CONFIG1H<3:0>) bits. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY (5) Clock Source Exit Delay LP, XT, HS HSPLL EC, RC ...
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... PIC18F87K90 FAMILY NOTES: DS39957B-page 66 Preliminary 2010 Microchip Technology Inc. ...
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... Brown-out Reset PWRT 32 s PWRT 11-Bit Ripple Counter LF-INTOSC 2010 Microchip Technology Inc. PIC18F87K90 FAMILY A simplified block diagram of the on-chip Reset circuit is shown in Figure 5-1. 5.1 RCON Register Device Reset events are tracked through the RCON register (Register 5-1). The lower five bits of the register indicate that a specific Reset event has occurred ...
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... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39957B-page 68 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 POR BOR bit Bit is unknown 2010 Microchip Technology Inc. ...
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... Power-on Reset. It also causes a Reset depending on which of the trip levels has been set: 1.8V, 2V, 2.7V or 3V. The typical (IB Low and Medium Power BOR will be 0.75 A and 3 A. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY In Zero-Power BOR (ZPBORMV), the module monitors the V voltage and re-arms the POR at about 2V ...
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... MCLR is kept low long enough, the PWRT will expire. Bringing MCLR high will begin execution immediately (Figure 5-5). This is useful for testing purposes, or for synchronizing more than one PIC18 device operating in parallel. T PWRT Preliminary 2010 Microchip Technology Inc. all depict time-out , V RISE < ...
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... FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET 2010 Microchip Technology Inc. PIC18F87K90 FAMILY T PWRT T PWRT , V RISE > 3. PWRT Preliminary ...
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... Table 5-2 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets, and WDT wake-ups. RCON Register ( POR Preliminary STKPTR Register BOR STKFUL STKUNF 2010 Microchip Technology Inc. ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for Reset value for specific condition. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for Reset value for specific condition. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for Reset value for specific condition. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for Reset value for specific condition. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for Reset value for specific condition. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, ...
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... PIC18F87K90 FAMILY NOTES: DS39957B-page 82 Preliminary 2010 Microchip Technology Inc. ...
Page 83
... Unimplemented Read as ‘0’ Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY The data EEPROM, for practical purposes, can be regarded as a peripheral device because it is addressed and accessed through a set of control registers ...
Page 84
... Flash memory, storing up to 16,384 single-word instructions • PIC18F66K90 and PIC18F86K90 — 64 Kbytes of Flash memory, storing up to 32,768 single-word instructions • PIC18F67K90 and PIC18F87K90 — 128 Kbytes of Flash memory, storing up to 65,536 single-word instructions The program memory maps for individual family members are shown in Figure 6-1. ...
Page 85
... TOSH TOSL 00h 1Ah 34h 2010 Microchip Technology Inc. PIC18F87K90 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers ...
Page 86
... TOS value. R/W-0 R/W-0 R/W-0 SP4 SP3 SP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) Preliminary and Instructions POP R/W-0 R/W-0 SP1 SP0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 87
... SUB1 RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK 2010 Microchip Technology Inc. PIC18F87K90 FAMILY 6.1.5 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
Page 88
... Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write Execute INST (PC) Fetch INST ( Execute INST ( Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Preliminary Internal Phase Clock Fetch INST ( Flush (NOP) Fetch SUB_1 Execute SUB_1 2010 Microchip Technology Inc. ...
Page 89
... MOVFF 1111 0100 0101 0110 0010 0100 0000 0000 ADDWF 2010 Microchip Technology Inc. PIC18F87K90 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...
Page 90
... When this instruction executes, it ignores the BSR completely. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. Preliminary 2010 Microchip Technology Inc. ...
Page 91
... BSR value, to access these registers. 2: These addresses are unused for devices with 32 Kbytes of program memory (PIC18FX5K90). For those devices, read these addresses at 00h. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Data Memory Map ...
Page 92
... This is data RAM which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. Preliminary (2) From Opcode 2010 Microchip Technology Inc. ...
Page 93
... Addresses, EF4h through F5Fh, are also used by SFRs, but are not part of the Access RAM. Users must always load the proper BSR value to access these registers. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY The SFRs can be classified into two sets: those associated with the “ ...
Page 94
... Addr. EFEh CCPR6H SSP2CON2 EFDh CCPR6L LCDREF EFCh CCP6CON LCDRL (3) EFBh LCDSE5 CCPR7H EFAh CCPR7L LCDSE4 EF9h CCP7CON LCDSE3 EF8h TMR4 LCDSE2 EF7h PR4 LCDSE1 EF6h T4CON LCDSE0 EF5h SSP2BUF LCDPS EF4h SSP2ADD LCDCON SSP2STAT SSP2CON1 2010 Microchip Technology Inc. ...
Page 95
... ANSEL23 ANSEL22 Note 1: Bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, bit is unimplemented. 2: Unimplemented on 64-pin devices (PIC18F6XK90). 3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K90). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 WERR — CS1 ...
Page 96
... CCP9M1 CCP9M0 --00 0000 xxxx xxxx xxxx xxxx CCP8M1 CCP8M0 --00 0000 xxxx xxxx xxxx xxxx CCP3M1 CCP3M0 0000 0000 xxxx xxxx xxxx xxxx P3DC1 P3DC0 0000 0000 PSS3BD1 PSS3BD0 0000 0000 CCP2M1 CCP2M0 0000 0000 xxxx xxxx 2010 Microchip Technology Inc. ...
Page 97
... RA7 RA6 Note 1: Bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, bit is unimplemented. 2: Unimplemented on 64-pin devices (PIC18F6XK90). 3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K90). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Bit 5 Bit 4 Bit 3 P2DC5 P2DC4 P2DC3 P2DC2 ...
Page 98
... CCP1IP RTCCIP 1111 1111 CMP2IF CMP1IF ---0 -000 — — ---- ---- HLVDL1 HLVDL0 0000 0000 CMP2IP CMP1IP ---1 -111 T1GSS1 T1GSS0 0000 0x00 OERR RX9D 0000 000x TRMT TX9D 0000 0010 xxxx xxxx 0000 0000 0000 0000 2010 Microchip Technology Inc. ...
Page 99
... Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) Note 1: Bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, bit is unimplemented. 2: Unimplemented on 64-pin devices (PIC18F6XK90). 3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K90). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Bit 5 Bit 4 Bit 3 T3GTM T3GSPM T3GGO/ ...
Page 100
... INT2IF INT1IF 1100 0000 INT3IP RBIP 1111 1111 INT0IF RBIF 0000 000x xxxx xxxx xxxxxxxx 0000 0000 0000 0000 0000 0000 --00 0000 0000 0000 0000 0000 ---0 0000 uu-0 0000 0000 0000 0000 0000 ---0 0000 2010 Microchip Technology Inc. ...
Page 101
... For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY It is recommended, therefore, that only BCF, BSF, ...
Page 102
... HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING LFSR FSR0, 100h ; NEXT CLRF POSTINC0 BTFSS FSR0H, 1 BRA NEXT CONTINUE Preliminary 2010 Microchip Technology Inc. and other Stack Pointer ; Clear INDF ; register then ; inc pointer ; All done with ; Bank1? ; NO, clear next ; YES, continue ...
Page 103
... FCCh. This means the contents of location, FCCh, will be added to that of the W register and stored back in FCCh. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY are mapped in the SFR space, but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair ...
Page 104
... Enabling the extended instruction set adds five additional two-word commands to the existing PIC18 instruction set: ADDFSR, CALLW, MOVSF, MOVSS and SUBFSR. These instructions are executed as described in Section 6.2.4 “Two-Word Instructions”. Preliminary 2010 Microchip Technology Inc. ...
Page 105
... Access Bank. Instead, the value is interpreted as an offset value to an Address Pointer specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY 6.6.2 INSTRUCTIONS AFFECTED BY ...
Page 106
... F00h Bank 15 F40h SFRs FFFh Data Memory BSR 000h 00000000 Bank 0 060h 100h Bank 1 001001da through Bank 14 F00h Bank 15 F40h SFRs FFFh Data Memory Preliminary 2010 Microchip Technology Inc. 00h 60h Valid range for ‘f’ FFh ffffffff FSR2L ffffffff ...
Page 107
... F00h BSR. F60h FFFh 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Remapping the Access Bank applies only to operations using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit = 1) will continue to use Direct Addressing as before. Any Indirect or Indexed ...
Page 108
... PIC18F87K90 FAMILY NOTES: DS39957B-page 108 Preliminary 2010 Microchip Technology Inc. ...
Page 109
... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: The Table Pointer register points to a byte in program memory. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY 7.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
Page 110
... The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Note: The EEIF interrupt flag bit (PIR6<4>) is set when the write is complete. It must be cleared in software. When set, Preliminary Table Latch (8-bit) TABLAT 2010 Microchip Technology Inc. ...
Page 111
... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-x R/W-0 ...
Page 112
... TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TBLPTR<21:6> TABLE READ – TBLPTR<21:0> Preliminary TBLPTRL 0 TABLE WRITE TBLPTR<5:0> 2010 Microchip Technology Inc. ...
Page 113
... WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVF WORD_ODD 2010 Microchip Technology Inc. PIC18F87K90 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
Page 114
... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts Preliminary 2010 Microchip Technology Inc. ...
Page 115
... Set WREN to enable byte writes 8. Disable the interrupts. 9. Write 0x55 to EECON2. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY The long write is necessary for programming the inter- nal Flash. Instruction execution is halted while in a long write cycle. The long write is terminated by the internal ...
Page 116
... TBLWT holding register. ; loop until buffers are full Preliminary 2010 Microchip Technology Inc. ...
Page 117
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: Bit 21 of TBLPTRU allows access to the device Configuration bits. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY ; point to Flash program memory ; access Flash program memory ; enable write to memory ...
Page 118
... PIC18F87K90 FAMILY NOTES: DS39957B-page 118 Preliminary 2010 Microchip Technology Inc. ...
Page 119
... EEPROM for read and write operations. EEADRH holds the two MSbs of the address; the upper 6 bits are ignored. The 10-bit range of the pair can address a memory range of 1024 bytes (00h to 3FFh). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY 8.2 EECON1 and EECON2 Registers Access to the data EEPROM is controlled by two registers: EECON1 and EECON2 ...
Page 120
... When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS39957B-page 120 R/W-0 R/W-x R/W-0 (1) FREE WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/S-0 R/S bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 121
... BSF INTCON, GIE BCF EECON1, WREN 2010 Microchip Technology Inc. PIC18F87K90 FAMILY execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware. After a write sequence has been initiated, EECON1, EEADRH:EEADR and EEDATA cannot be modified ...
Page 122
... Loop to refresh array ; Read current address ; ; Write 55h ; ; Write 0AAh ; Set WR bit to begin write ; Wait for write to complete ; Increment address ; Not zero again ; Increment the high address ; Not zero again ; Disable writes ; Enable interrupts Preliminary information (e.g., program 2010 Microchip Technology Inc. ...
Page 123
... EEDATA EEPROM Data Register EECON2 EEPROM Control Register 2 (not a physical register) EECON1 EEPGD CFGS Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — ...
Page 124
... PIC18F87K90 FAMILY NOTES: DS39957B-page 124 Preliminary 2010 Microchip Technology Inc. ...
Page 125
... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply 2010 Microchip Technology Inc. PIC18F87K90 FAMILY EXAMPLE 9-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 9-2: MOVF ARG1, W MULWF ARG2 BTFSC ...
Page 126
... RES2 WREG ; RES3 ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products RES2 WREG ; RES3 ARG2H ARG2H:ARG2L neg? ; no, check ARG1 ARG1L RES2 ; ARG1H RES3 ; ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H RES3 2010 Microchip Technology Inc. ...
Page 127
... Individual interrupts can be disabled through their corresponding enable bits. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ...
Page 128
... PEIE/GIEL IPEN TMR0IF IPEN TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP Preliminary 2010 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL ...
Page 129
... Note 1: A mismatch condition will continue to set this bit. Reading PORTB, and then waiting one additional instruction cycle, will end the mismatch condition and allow the bit to be cleared. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Note: Interrupt flag bits are set when an interrupt ...
Page 130
... This feature allows for software polling. DS39957B-page 130 R/W-1 R/W-1 R/W-1 INTEDG2 INTEDG3 TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 131
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 ...
Page 132
... R-0 R/W-0 R/W-0 TX1IF SSP1IF TMR1GIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 133
... TMR3 register overflowed (must be cleared in software TMR3 register did not overflow bit 0 TMR3GIF: TMR3 Gate Interrupt Flag bit 1 = Timer gate interrupt occurred (must be cleared in software timer gate interrupt occurred 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-0 R/W-0 BCL2IF BCL1IF HLVDIF U = Unimplemented bit, read as ‘ ...
Page 134
... RTCCIF: RTCC Interrupt Flag bit 1 = RTCC interrupt occured (must be cleared in software RTCC interrupt occured DS39957B-page 134 R-0 R/W-0 R/W-0 TX2IF CTMUIF CCP2IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 CCP1IF RTCCIF bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 135
... Compare Mode TMR register compare match occurred (must be cleared in software TMR register compare match occurred PWM Mode Not used in PWM mode. Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K90). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-0 R/W-0 CCP7IF CCP6IF CCP5IF U = Unimplemented bit, read as ‘ ...
Page 136
... Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K90). DS39957B-page 136 R/W-0 R/W-0 R/W-0 (1) (1) TMR8IF TMR7IF TMR6IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) (1) Preliminary R/W-0 R/W-0 TMR5IF TMR4IF bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 137
... CMP2IF: CMP2 Interrupt Flag bit 1 = CMP2 interrupt occurred (must be cleared in software CMP2 interrupt occurred bit 0 CMP1IF: CM1 Interrupt Flag bit 1 = CMP1 interrupt occurred (must be cleared in software CMP1 interrupt occurred 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 U-0 R/W-0 EEIF — ...
Page 138
... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt DS39957B-page 138 R/W-0 R/W-0 R/W-0 TX1IE SSP1IE TMR1GIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 139
... Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 TMR3GIE: Timer3 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-0 R/W-0 BCL2IE BCL1IE HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 140
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 R/W-0 CCP7IE CCP6IE CCP5IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 CCP1IE RTCCIE bit Bit is unknown R/W-0 R/W-0 CCP4IE CCP3IE bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 141
... Disables the TMR5 overflow interrupt bit 0 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enables the TMR4 to PR4 match interrupt 0 = Disables the TMR4 to PR4 match interrupt Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K90). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-0 R/W-0 (1) (1) ...
Page 142
... CMP1IE: CMP1 Enable bit 1 = Interrupt is enabled 0 = interrupt is disabled DS39957B-page 142 R/W-0 U-0 R/W-0 EEIE — CMP3IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 CMP2IE CMP1IE bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 143
... TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-1 R/W-1 R/W-1 TX1IP SSP1IP TMR1GIP U = Unimplemented bit, read as ‘0’ ...
Page 144
... TMR3GIP: TMR3 Gate Interrupt Priority bit 1 = High priority 0 = Low priority DS39957B-page 144 R/W-1 R/W-1 R/W-1 BCL2IP BCL1IP HLVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 TMR3IP TMR3GIP bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 145
... Bit is set bit 7-0 CCP10IP:CCP3IP: CCP<10:3> Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: CCP10IP and CCP9IP are unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K90). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R-1 R/W-1 R/W-1 TX2IP CTMUIP CCP2IP U = Unimplemented bit, read as ‘ ...
Page 146
... Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K90). DS39957B-page 146 R/W-1 R/W-1 R/W-1 (1) (1) TMR8IP TMR7IP TMR6IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) (1) Preliminary R/W-1 R/W-1 TMR5IP TMR4IP bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 147
... Low priority bit 1 CMP2IP: CMP2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CMP1IP: CMP1 Interrupt Priority bit 1 = High priority 0 = Low priority 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-1 U-0 R/W-1 EEIE — CMP3IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 148
... For details of bit operation, see Register 5-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 5-1. DS39957B-page 148 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 POR BOR bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 149
... MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS 2010 Microchip Technology Inc. PIC18F87K90 FAMILY The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON<5>). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit, TMR0IP (INTCON2<2>). For further details on the Timer0 module, see Section 12.0 “Timer0 Module” ...
Page 150
... TMR3GIF 75 CCP1IF RTCCIF 75 CCP4IF CCP3IF 75 TMR5IF TMR4IF 75 CMP2IF CMP1IF 75 TMR2IE TMR1IE 75 TMR3IE TMR3GIE 75 CCP1IE RTCCIE 75 CCP4IE CCP3IE 75 TMR5IE TMR4IE 75 CMP2IE CMP1IE 78 TMR2IP TMR1IP 75 TMR3IP TMR3GIP 75 CCP1IP RTCCIP 75 CCP4IP CCP3IP 75 TMR5IP TMR4IP 74 CMP2IE CMP1IE 75 PD POR BOR 74 2010 Microchip Technology Inc. ...
Page 151
... TRIS Latch RD TRIS PORT 2010 Microchip Technology Inc. PIC18F87K90 FAMILY 11.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V All of the digital ports are 5 ...
Page 152
... SSP2OD: SPI2 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled DS39957B-page 152 FIGURE 11-2: USING THE OPEN-DRAIN OUTPUT (USART SHOWN AS EXAMPLE) 3.3V PIC18F67K90 V DD (at logic ‘1’) U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ...
Page 153
... Open-drain capability is enabled 0 = Open-drain capability is disabled bit 0 CCP3OD: ECCP3 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled Note 1: Unimplemented on PIC18FX5K90 devices. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-0 R/W-0 CCP7OD CCP6OD CCP5OD U = Unimplemented bit, read as ‘0’ ...
Page 154
... Setting these registers makes the corresponding pins analog and clearing the registers makes the ports digi- tal. For details on these registers, see Section 23.0 “12-Bit Analog-to-Digital Converter (A/D) Module”. Preliminary 2010 Microchip Technology Inc. U-0 R/W-0 — CTMUDS bit 0 ...
Page 155
... Note: RA5 and RA<3:0> are configured as analog inputs on any Reset and are read as ‘0’. RA4 is configured as a digital input. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY OSC2/CLKO/RA6 and serve as the external circuit connections for the exter- ...
Page 156
... Main oscillator input connection (HS, XT and LP modes). I ANA Main external clock source input (EC modes). O DIG LATA<7> data output; disabled when OSC2 Configuration bit is set. I TTL PORTA<7> data input; disabled when OSC2 Configuration bit is set. Preliminary Description /4, EC and INTOSC modes). OSC 2010 Microchip Technology Inc. ...
Page 157
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘x’. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Bit 5 Bit 4 ...
Page 158
... The RB<5:0> pins also are multiplexed with LCD seg- ment drives that are controlled by bits in the registers, LCDSE1 and LCDSE3. I/O port functionality is only available when the LCD segments are disabled. Preliminary 2010 Microchip Technology Inc. wake the device from delay ...
Page 159
... Legend Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY I/O I/O ...
Page 160
... TMR0IF TMR0IP INT3IE INT2IE INT1IE INT3IF SE13 SE12 SE11 SE10 SE29 SE28 SE27 SE26 Preliminary Reset Bit 1 Bit 0 Values on Page: RB1 RB0 76 LATB1 LATB0 76 TRISB1 TRISB0 76 INT0IF RBIF 73 INT3IP RBIP 73 INT2IF INT1IF 73 SE09 SE08 81 SE25 SE24 81 2010 Microchip Technology Inc. ...
Page 161
... TRIS bit settings. Note: These pins are configured as digital inputs on any device Reset. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins. The RC< ...
Page 162
... Synchronous serial data output (EUSART module); takes priority over port data. DIG Synchronous serial data input (EUSART module); user must configure as an input. ST Synchronous serial clock input (EUSART module). ANA LCD Segment 27 output; disables all other pin functions. Preliminary Description 2010 Microchip Technology Inc. ...
Page 163
... LCDSE4 SE39 SE38 ODCON1 SSP1OD CCP2OD CCP1OD Legend: Shaded cells are not used by PORTC. Note 1: Unimplemented on PIC18F6XK90 devices, read as ‘0’. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY I/O Type DIG LATC<7> data output. ST PORTC<7> data input. ST Asynchronous serial receive data input (EUSART module). ...
Page 164
... CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs Preliminary 2010 Microchip Technology Inc and SPI functionality on ...
Page 165
... O = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY I/O I/O Type O DIG LATD<0> data output. ...
Page 166
... DS39957B-page 166 Bit 4 Bit 3 Bit 2 RD4 RD3 RD2 LATD4 LATD3 LATD2 TRISD4 TRISD3 TRISD2 SE04 SE03 SE02 (1) — — RTSECSEL1 RTSECSEL0 Preliminary Reset Bit 1 Bit 0 Values on Page: RD1 RD0 76 LATD1 LATD0 76 TRISD1 TRISD0 76 SE01 SE00 81 — 78 2010 Microchip Technology Inc. ...
Page 167
... If the LCD bias voltages are generated using the internal resistor ladder, the LCDBIASx pins are also available as I/O ports (RE0, RE1 and RE2). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Pins, RE2, RE1 and RE0, are multiplexed with the functions of LCDBIAS3, LCDBIAS2 and LCDBIAS1. ...
Page 168
... PORTE<6> data input. O ANA LCD Common 3 output; disables all other outputs. O — ECCP1 PWM Output B. May be configured for tri-state during Enhanced PWM shutdown events. O DIG CCP6 Compare/PWM output. Takes priority over port data CCP9 capture input. Preliminary Description 2010 Microchip Technology Inc. ...
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... CCP2OD CCP1OD ODCON2 CCP10OD CCP9OD CCP8OD CCP7OD CCP6OD PADCFG1 RDPU REPU RJPU Legend: Shaded cells are not used by PORTE. Note 1: Not available on 64-pin devices. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY I/O I/O Type O DIG LATE<7> data output PORTE<7> data input. ...
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... Make AN6, AN7 and AN5 digital MOVWF ANCON1 ; MOVLW 0F0h ; Make AN8, AN9, AN10 and AN11 digital MOVWF ANCON2 ; Set PORTF as digital I/O MOVLW 0CEh ; Value used to ; initialize data ; direction MOVWF TRISF ; Set RF3:RF1 as inputs ; RF5:RF4 as outputs ; RF7:RF6 as inputs Preliminary 2010 Microchip Technology Inc. ...
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... Legend Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY I/O I/O ...
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... CVRR CVRSS CVR3 CVR2 SE21 SE20 SE19 SE18 SE29 SE28 SE27 SE26 Preliminary Reset Bit 1 Bit 0 Values on Page: RF1 — 76 LATF1 — 76 TRISF1 — 76 ANSEL1 ANSEL0 79 ANSEL8 79 — — 75 CVR1 CVR0 75 SE17 SE16 81 SE25 SE24 81 2010 Microchip Technology Inc. ...
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... Legend Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTG pin ...
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... Bit 4 Bit 3 Bit 2 (1) RG5 RG4 RG3 RG2 — TRISG4 TRISG3 TRISG2 SE29 SE28 SE27 SE26 — — — Preliminary Description Reset Bit 1 Bit 0 Values on Page: RG1 RG0 76 TRISG1 TRISG0 76 SE25 SE24 81 79 — SSP2OD 79 79 2010 Microchip Technology Inc. ...
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... PORTH pins are multiplexed ADC/CCP/Comparator and LCD segment controlled by the LCDSE5 register. I/O port functions are only available when the segments are disabled. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY EXAMPLE 11-8: CLRF PORTH CLRF LATH BANKSEL ANCON2 MOVLW 0Fh MOVWF ...
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... CCP8 compare/PWM output. Takes priority over port data CCP8 capture input. O — ECCP3 PWM Output B. May be configured for tri-state during Enhanced PWM. I ANA A/D Input Channel 13. Default input configuration on POR. Does not affect digital input. I ANA Comparator 2 Input D. Preliminary Description 2010 Microchip Technology Inc. ...
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... SE46 ANCON1 ANSEL15 ANSEL14 ANSEL13 ANSEL12 ANSEL11 ANSEL10 ANSEL9 ANCON2 ANSEL23 ANSEL22 ANSEL21 ANSEL20 ANSEL19 ANSEL18 ANSEL17 ANSEL16 ODCON2 CCP10OD CCP9OD CCP8OD CCP7OD CCP6OD CCP5OD CCP4OD CCP3OD 2010 Microchip Technology Inc. PIC18F87K90 FAMILY I/O I/O Type O DIG LATH<6> data output. ...
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... Reset. EXAMPLE 11-9: INITIALIZING PORTJ CLRF PORTJ ; Initialize PORTJ by ; clearing output latches CLRF LATJ ; Alternate method ; to clear output latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISJ ; Set RJ3:RJ0 as inputs ; RJ5:RJ4 as output ; RJ7:RJ6 as inputs Preliminary 2010 Microchip Technology Inc. ...
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... TRISJ5 LCDSE4 SE39 SE38 SE37 PADCFG1 RDPU REPU RJPU Legend: Shaded cells are not used by PORTJ. Note 1: Unimplemented on PIC18F6XK90 devices, read as ‘0’. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY I/O I/O Type DIG LATJ<0> data output PORTJ<0> data input. I DIG LATJ< ...
Page 180
... PIC18F87K90 FAMILY NOTES: DS39957B-page 180 Preliminary 2010 Microchip Technology Inc. ...
Page 181
... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value 2010 Microchip Technology Inc. PIC18F87K90 FAMILY The T0CON register (Register 12-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. Figure 12-1 provides a simplified block diagram of the Timer0 module in 8-bit mode ...
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... Sync with Internal TMR0L Clocks Delay Preliminary ). There is a delay between OSC Set TMR0L TMR0IF on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus 2010 Microchip Technology Inc. ...
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... INTCON GIE/GIEH PEIE/GIEL TMR0IE T0CON TMR0ON T08BIT Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY 12.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution ...
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... PIC18F87K90 FAMILY NOTES: DS39957B-page 184 Preliminary 2010 Microchip Technology Inc. ...
Page 185
... Note 1: The F clock source should not be selected if the timer will be used with the ECCP capture/compare features. OSC 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Figure 13-1 displays a simplified block diagram of the Timer1 module. The SOSC oscillator can also be used as a low-power clock source for the microcontroller in power-managed operation ...
Page 186
... Timer1 gate pin Note 1: Programming the T1GCON prior to T1CON is recommended. DS39957B-page 186 (T1GCON), (1) R/W-0 R/W-0 R-x T1GSPM T1GGO/T1DONE T1GVAL U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 T1GSS1 T1GSS0 bit Bit is unknown 2010 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F87K90 FAMILY 13.3.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 module may work as a timer or a counter. When enabled to count, Timer1 is incremented on the rising edge of the external clock input, T1CKI. Either of these external clock sources can be synchronized to the ...
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... T1CLK TMR1L Q D TMR1CS<1:0> T1SYNC Prescaler OSC T1CKPS<1:0> Internal 01 Clock F /4 OSC Internal 00 Clock Preliminary 0 T1GVAL Data Bus T1GCON Q1 EN Interrupt Set TMR1GIF det TMR1GE Synchronized 0 Clock Input 1 (3) Synchronize det OSC Sleep Input Internal Clock 2010 Microchip Technology Inc. ...
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... PIC18F87K90 12 pF SOSCI XTAL 32.768 kHz SOSCO Note: See the Notes with Table 13-2 for additional information about capacitor selection. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY TABLE 13-2: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Oscillator Freq. Type LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
Page 190
... Timer1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled or disabled by setting or clearing the Timer1 Interrupt Enable bit, TMR1IE (PIE1<0>). Preliminary OSCILLATOR CIRCUIT WITH GROUNDED GUARD RING OSC1 OSC2 RC0 RC1 RC2 2010 Microchip Technology Inc. ...
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... Timer1 gate circuitry. This is also referred to as Timer1 gate count enable. Timer1 gate can also be driven by multiple selectable sources. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY 13.8.1 TIMER1 GATE COUNT ENABLE The Timer1 Gate Enable mode is enabled by setting the TMR1GE bit of the T1GCON register ...
Page 192
... CMP1OUT (CMSTAT<5>) bit. 13.8.2.4 Comparator 2 Output Gate Operation The output of Comparator 2 can be internally supplied to the Timer1 gate circuitry. After setting up Comparator 2 with the CM2CON register, Timer1 will increment depending on the transition of the CMP2OUT (CMSTAT<6>) bit. Preliminary 2010 Microchip Technology Inc ...
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... T1G_IN T1CKI T1GVAL Timer1 2010 Microchip Technology Inc. PIC18F87K90 FAMILY The T1GVAL bit (T1GCON<2>) indicates when the Toggled mode is active and the timer is counting. The Timer1 Gate Toggle mode is enabled by setting the T1GTM bit (T1GCON<5>). When T1GTM is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured ...
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... The value is stored in the T1GVAL bit (T1GCON<2>). This bit is valid even when the Timer1 gate is not enabled (TMR1GE bit is cleared). Cleared by Hardware on Falling Edge of T1GVAL Set by Hardware on Falling Edge of T1GVAL Preliminary 2010 Microchip Technology Inc. Cleared by Software ...
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... OSCCON2 — SOSCRUN CCPTMRS0 C3TSEL1 C3TSEL0 C2TSEL2 C2TSEL1 C2TSEL0 C1TSEL2 C1TSEL1 C1TSEL0 CCPTMRS1 C7TSEL1 C7TSEL0 CCPTMRS2 — — Legend: Shaded cells are not used by the Timer1 module. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Set by Hardware on Falling Edge of T1GVAL Bit 5 Bit 4 ...
Page 196
... PIC18F87K90 FAMILY NOTES: DS39957B-page 196 Preliminary 2010 Microchip Technology Inc. ...
Page 197
... T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 2010 Microchip Technology Inc. PIC18F87K90 FAMILY The value of TMR2 is compared to that of the Period reg- ister, PR2, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output ...
Page 198
... Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TX1IF SSP1IF TMR1GIF TX1IE SSP1IE TMR1GIE TX1IP SSP1IP TMR1GIP Preliminary Set TMR2IF TMR2 Output (to PWM or MSSPx) PR2 8 Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 73 TMR2IF TMR1IF 75 TMR2IE TMR1IE 75 TMR2IP TMR1IP 2010 Microchip Technology Inc. ...
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... Timer3, Timer5 or Timer7 module. For example, the control register is named TxCON and refers to T3CON, T5CON and T7CON. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY A simplified block diagram of the Timer3/5/7 module is shown in Figure 15-1. The Timer3/5/7 module is controlled through the TxCON register (Register 15-1) ...
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... ECCP capture/compare OSC features. DS39957B-page 200 R/W-0 R/W-0 R/W-0 TxCKPS0 SOSCEN TxSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ) OSC /4) OSC Preliminary R/W-0 R/W-0 RD16 TMRxON bit Bit is unknown 2010 Microchip Technology Inc. ...