PIC16C72-04I/SS Microchip Technology, PIC16C72-04I/SS Datasheet - Page 34
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PIC16C72-04I/SS
Manufacturer Part Number
PIC16C72-04I/SS
Description
IC MCU OTP 2KX14 A/D PWM 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16C72-04SO.pdf
(289 pages)
4.PIC16C72-04SO.pdf
(125 pages)
5.PIC16C72-04SO.pdf
(8 pages)
Specifications of PIC16C72-04I/SS
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
For Use With
309-1025 - ADAPTER 28-SSOP TO 28-DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
PIC16C72 Series
7.1
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1. An event is defined as:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value will be lost.
7.1.1
In Capture mode, the RC2/CCP1 pin should be config-
ured as an input by setting the TRISC<2> bit.
FIGURE 7-2:
7.1.2
Timer1 must be running in timer mode or synchronized
counter mode for the CCP module to use the capture
feature. In asynchronous counter mode, the capture
operation may not work.
7.1.3
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
DS39016A-page 34
RC2/CCP1
Pin
Note:
Capture Mode
CCP PIN CONFIGURATION
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT
If the RC2/CCP1 is configured as an out-
put, a write to the port can cause a capture
condition.
edge detect
Q’s
Prescaler
1, 4, 16
and
CCP1CON<3:0>
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Set flag bit CCP1IF
(PIR1<2>)
Capture
Enable
CCPR1H
TMR1H
CCPR1L
TMR1L
Preliminary
7.1.4
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in capture mode,
the prescaler counter is cleared. This means that any
reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the first capture may be from
a non-zero prescaler. Example 7-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 7-1:
CLRF
MOVLW
MOVWF
CCP1CON
NEW_CAPT_PS
CCP1CON
CCP PRESCALER
CHANGING BETWEEN
CAPTURE PRESCALERS
;Turn CCP module off
;Load the W reg with
; the new prescaler
; mode value and CCP ON
;Load CCP1CON with this
; value
1998 Microchip Technology Inc.