PIC18LF2420-I/SP Microchip Technology, PIC18LF2420-I/SP Datasheet - Page 6

IC MCU FLASH 8KX16 28-DIP

PIC18LF2420-I/SP

Manufacturer Part Number
PIC18LF2420-I/SP
Description
IC MCU FLASH 8KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18LF2420-I/SP

Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
25
Interface Type
I2C/SPI/USART
On-chip Adc
10-chx10-bit
Number Of Timers
4
Core
PIC
Processor Series
PIC18LF
Maximum Clock Frequency
40 MHz
Data Ram Size
768 B
Data Rom Size
256 B
Mounting Style
Through Hole
Height
3.3 mm
Length
34.67 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Width
7.24 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
PIC18F2420/2520/4420/4520
19. Module: EUSART
20. Module: Timer1/Timer3
DS80209H-page 6
When performing back-to-back transmission in 9-bit
mode (TX9D bit in the TXSTA register is set), the
second byte may be corrupted if it is written into
TXREG immediately after the TMRT bit is set.
Work around
Execute a software delay, at least one-half the
transmission’s bit time, after TMRT is set and prior
to writing subsequent bytes into TXREG.
Date Codes that pertain to this issue:
All engineering and production devices.
When Timer1 or Timer3 is configured for external
clock source, and the CCPxCON register is
configured with 0x0B (Compare mode, trigger
special event), the timer is not reset on a Special
Event Trigger.
Work around
Modify firmware to reset the Timer1/Timer3
registers upon detection of the compare match
condition — TMRxL and TMRxH.
Date Codes that pertain to this issue:
All engineering and production devices.
21. Module: Timer1/Timer3
22. Module: Timer1/Timer3
When Timer1 or Timer3 is in External Clock
Synchronized mode and the external clock period
is between 1 and 2 T
be skipped.
Work around
Avoid using an external clock with a period (1/
frequency) between 1 and 2 T
Date Codes that pertain to this issue:
All engineering and production devices.
When Timer1/Timer3 is operating in 16-bit mode
and the prescale setting is not 1:1, a write to the
TMR1H/TMR3H Buffer registers may lengthen the
duration of the period between the increments of
the timer for the period in which TMR1H/TMR3H
was written.
Work around
Two work arounds are available: 1) Stop Timer1/
Timer3
registers; 2) Write TMR1L/TMR3L immediately
after writing TMR1H/TMR3H.
Date Codes that pertain to this issue:
All engineering and production devices.
before
writing
© 2008 Microchip Technology Inc.
CY
, interrupts will occasionally
the
CY
.
TMR1H/TMR3H

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