PIC16F876-04E/SO Microchip Technology, PIC16F876-04E/SO Datasheet - Page 89

• Manufacturer Part Number: PIC16F876-04E/SO
• Description: IC MCU FLASH 8KX14 EE 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F876-04E/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Core: PIC
• Processor Series: PIC16F
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Data Ram Size: 368 B
• Data Rom Size: 256 B
• On-chip Adc: Yes
• Number Of Programmable I/os: 22
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 5
• Height: 2.31 mm
• Interface Type: MSSP, PSP, USART
• Length: 17.87 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4 V
• Width: 7.49 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC16F87604E/SO

9.2.14
A STOP bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2<2>). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sam-
pled low, the baud rate generator is reloaded and
counts down to 0. When the baud rate generator times
out, the SCL pin will be brought high, and one T
(baud rate generator rollover count) later, the SDA pin
will be de-asserted. When the SDA pin is sampled high
FIGURE 9-17:
2001 Microchip Technology Inc.
STOP CONDITION TIMING
SCL
SDA
Note: T
Write to SSPCON2
Falling edge of
9th clock
BRG
STOP CONDITION RECEIVE OR TRANSMIT MODE
ACK
= one baud rate generator period.
Set PEN
SDA asserted low before rising edge of clock
to setup STOP condition
T
T
BRG
BRG
BRG
T
SCL brought high after T
BRG
SCL = 1 for T
after SDA sampled high. P bit (SSPSTAT<4>) is set.
P
T
BRG
while SCL is high, the P bit (SSPSTAT<4>) is set. A
T
set (Figure 9-17).
Whenever the firmware decides to take control of the
bus, it will first determine if the bus is busy by checking
the S and P bits in the SSPSTAT register. If the bus is
busy, then the CPU can be interrupted (notified) when
a STOP bit is detected (i.e., bus is free).
9.2.14.1
If the user writes the SSPBUF when a STOP sequence
is in progress, then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
BRG
BRG
PEN bit (SSPCON2<2>) is cleared by
later, the PEN bit is cleared and the SSPIF bit is
hardware and the SSPIF bit is set
, followed by SDA = 1 for T
BRG
WCOL Status Flag
PIC16F87X
BRG
DS30292C-page 87