PIC16LF737-I/SO Microchip Technology, PIC16LF737-I/SO Datasheet - Page 96
![IC PIC MCU FLASH 4KX14 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC16LF737-I/SO
Manufacturer Part Number
PIC16LF737-I/SO
Description
IC PIC MCU FLASH 4KX14 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF737-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
AUSART, CCP, I2C, MSSP, SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
25
Number Of Timers
8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Data Rom Size
368 B
Height
2.31 mm
Length
17.87 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Width
7.49 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC16LF737-I/SOR
PIC16LF737-I/SOR
PIC16LF737-I/SOR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16LF737-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 96 of 276
- Download datasheet (6Mb)
PIC16F7X7
10.3.1
The MSSP module has four registers for SPI mode
operation. These are:
• MSSP Control Register (SSPCON)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
SSPCON and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON
register is readable and writable. The lower 6 bits of
the SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
REGISTER 10-1:
DS30498C-page 94
accessible
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
REGISTERS
SSPSTAT: MSSP STATUS (SPI MODE) REGISTER (ADDRESS 94h)
bit 7
SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
CKE: SPI Clock Edge Select bit
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
D/A: Data/Address bit
Used in I
P: Stop bit
Used in I
S: Start bit
Used in I
R/W: Read/Write bit Information
Used in I
UA: Update Address bit
Used in I
BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Legend:
R = Readable bit
-n = Value at POR
R/W-0
Note:
SMP
2
2
2
2
2
C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.
C mode only.
C mode only.
C mode only.
C mode only.
Polarity of clock state is set by the CKP bit (SSPCON1<4>).
R/W-0
CKE
R-0
D/A
W = Writable bit
‘1’ = Bit is set
R-0
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not double-
buffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
P
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R-0
S
R/W
R-0
2004 Microchip Technology Inc.
x = Bit is unknown
R-0
UA
R-0
BF
bit 0
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