PIC16C72-10I/SS Microchip Technology, PIC16C72-10I/SS Datasheet - Page 16
![IC MCU OTP 2KX14 A/D PWM 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC16C72-10I/SS
Manufacturer Part Number
PIC16C72-10I/SS
Description
IC MCU OTP 2KX14 A/D PWM 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16C72-04SO.pdf
(289 pages)
4.PIC16C72-04SO.pdf
(125 pages)
5.PIC16C72-04SO.pdf
(8 pages)
Specifications of PIC16C72-10I/SS
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
For Use With
309-1025 - ADAPTER 28-SSOP TO 28-DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
PIC16C72 Series
2.3.1
The stack allows a combination of up to 8 program calls
and interrupts to occur. The stack contains the return
address from this branch in program execution.
Midrange devices have an 8 level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not modified when the stack is PUSHed or
POPed.
After the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on). An example of the overwriting of the stack is
shown in Figure 2-10.
FIGURE 2-10: STACK MODIFICATION
DS39016A-page 16
Push1 Push9
Push2 Push10
Push3
Push4
Push5
Push6
Push7
Push8
STACK
STACK
Top of STACK
Preliminary
rupt) is executed, the entire 13-bit PC is pushed onto
the
PCLATH<4:3> bits are not required for the return
instructions (which POPs the address from the stack).
2.4
The CALL and GOTO instructions provide 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALL or GOTO instruction
the upper 2 bits of the address are provided by
PCLATH<4:3>. When doing a CALL or GOTO instruction,
the user must ensure that the page select bits are pro-
grammed so that the desired program memory page is
addressed. If a return from a CALL instruction (or inter-
Note:
stack.
Program Memory Paging
PIC16C72 Series devices ignore paging
bit PCLATH<4>. The use of PCLATH<4>
as a general purpose read/write bit is not
recommended since this may affect
upward compatibility with future products.
Therefore,
1998 Microchip Technology Inc.
manipulation
of
the