PIC18F87K90-I/PTRSL Microchip Technology, PIC18F87K90-I/PTRSL Datasheet
PIC18F87K90-I/PTRSL
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PIC18F87K90-I/PTRSL Summary of contents
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... Microcontrollers with LCD Driver and 2010 Microchip Technology Inc. PIC18F87K90 Family Data Sheet 64/80-Pin, High-Performance nanoWatt XLP Technology Preliminary DS39957B ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F86K90 64K 4K PIC18F87K90 128K 4K 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Peripheral Highlights: • Ten or eight CCP/ECCP modules: - Seven Capture/Compare/PWM (CCP) modules - Three Enhanced Capture/Compare/PWM (ECCP) modules • Eleven 8/16-Bit Timer/Counter modules: - Timer0 – 8/16-bit timer/counter with 8-bit programmable prescaler - Timer1,3,5,7 – ...
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... PIC18F87K90 FAMILY Special Microcontroller Features: • Operating Voltage Range: 1.8V to 5.5V • On-Chip 3.3V Regulator • Operating Speed MHz • 128 Kbytes On-Chip Flash Program Memory • Data EEPROM of 1,024 Bytes • General Purpose Registers (SRAM) • 10,000 Erase/Write Cycle Flash Program Memory, Typical • ...
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... RG3/CCP4/AN17/P3D/C3INB MCLR/RG5 RG4/SEG26/RTCC/T7CKI/T5G/CCP5/AN16/P1D/C3INC V /V DDCORE RF7/AN5/SS1/SEG25 RF6/AN11/SEG24/C1INA RF5/AN10/CV /SEG23/C1INB REF RF4/AN9/SEG22/C2INA RF3/AN8/SEG21/C2INB/CTMUI RF2/AN7/C1OUT/SEG20 Note 1: The ECCP2 pin placement depends on the CCP2MX Configuration bit setting. 2: Not available in the PIC18F65K90 and PIC18F85K90. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY PIC18F65K90 6 7 PIC18F66K90 8 PIC18F67K90 V ...
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... PIC18F87K90 FAMILY Pin Diagrams – PIC18F8XK90 80-Pin TQFP RH2/SEG45/AN21 RH3/SEG44/AN20 RE1/LCDBIAS2/P2C RE0/LCDBIAS1/P2D RG0/ECCP3/P3A RG1/TX2/CK2/AN19/C3OUT RG2/RX2/DT2/AN18/C3INA RG3/CCP4/AN17/P3D/C3INB MCLR/RG5 RG4/SEG26/RTCC/T7CKI/T5G/CCP5/AN16/P1D/C3INC DDCORE CAP RF7/AN5/SS1/SEG25 RF6/AN11/SEG24/C1INA RF5/AN10/CV /SEG23/C1INB REF RF4/AN9/SEG22/C2INA RF3/AN8/SEG21/C2INB/CTMUI RF2/AN7/C1OUT/SEG20 (3) RH7/SEG43/CCP6 /P1B/AN15 (3) RH6/SEG42/CCP7 /P1C/AN14/C1INC Note 1: The ECCP2 pin placement depends on the CCP2MX Configuration bit setting. ...
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... Instruction Set Summary .......................................................................................................................................................... 449 30.0 Development Support............................................................................................................................................................... 499 31.0 Electrical Characteristics .......................................................................................................................................................... 503 32.0 Packaging Information.............................................................................................................................................................. 541 Appendix A: Revision History............................................................................................................................................................. 549 Appendix B: Migration From PIC18F85J90 and PIC18F87J90 to PIC18F87K90 .............................................................................. 549 Index ................................................................................................................................................................................................. 551 The Microchip Web Site ..................................................................................................................................................................... 563 Customer Change Notification Service .............................................................................................................................................. 563 Customer Support .............................................................................................................................................................................. 563 Reader Response ...
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... PIC18F87K90 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...
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... Core Features 1.1.1 nanoWatt TECHNOLOGY All of the devices in the PIC18F87K90 family incorpo- rate a range of features that can significantly reduce power consumption during operation. Key items include: • Alternate Run Modes: By clocking the controller from the Timer1 source or the internal RC oscillator, power consumption during code execution can be reduced ...
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... January 1, 2000 to 23:59:59 on December 31, 2099. 1.4 Details on Individual Family Members Devices in the PIC18F87K90 family are available in 64-pin and 80-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in these ways: • ...
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... Timers Comparators CTMU RTCC Capture/Compare/PWM (CCP) Modules Enhanced CCP (ECCP) Modules Serial Communications 12-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set Packages 2010 Microchip Technology Inc. PIC18F87K90 FAMILY PIC18F65K90 PIC18F66K90 DC – 64 MHz 32K 64K 16,384 32,768 Ports 132 (33 SEGs x 4 COMs) ...
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... PIC18F87K90 FAMILY FIGURE 1-1: PIC18F6XK90 (64-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic 21 20 Address Latch Program Memory Data Latch 8 Table Latch ROM Latch Instruction Bus <16> Instruction Decode and Timing Power-up OSC2/CLKO Generation OSC1/CLKI INTRC Oscillator Oscillator Start-up Timer 16 MHz Power-on ...
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... See Table 1-3 for I/O port pin descriptions. 2: RA6 and RA7 are only available as digital I/O in select oscillator modes. See Section 3.0 “Oscillator Configurations” for more information. 3: Unimplemented on the PIC18F85K90. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Data Bus<8> Data Latch 8 8 Data Memory (2/4 Kbytes) ...
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... PIC18F87K90 FAMILY TABLE 1-3: PIC18F6XK90 PINOUT I/O DESCRIPTIONS Pin Number Pin Name QFN/TQFP MCLR/RG5 7 MCLR RG5 OSC1/CLKI/RA7 39 OSC1 CLKI RA7 OSC2/CLKO/RA6 40 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power C™ C/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. ...
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... Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Pin Buffer Type Type PORTA is a bidirectional I/O port. ...
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... PIC18F87K90 FAMILY TABLE 1-3: PIC18F6XK90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name QFN/TQFP RB0/INT0/SEG30/FLTO 48 RB0 INT0 SEG30 FLTO RB1/INT1/SEG8 47 RB1 INT1 SEG8 RB2/INT2/SEG9/CTED1 46 RB2 INT2 CTED1 SEG9 RB3/INT3/SEG10/CTED2/ 45 ECCP2/P2A RB3 INT3 SEG10 CTED2 ECCP2 P2A RB4/KBI0/SEG11 44 RB4 KBI0 SEG11 RB5/KBI1/SEG29/T3CKI/ ...
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... Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port. ...
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... PIC18F87K90 FAMILY TABLE 1-3: PIC18F6XK90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name QFN/TQFP RD0/SEG0/CTPLS 58 RD0 SEG0 CTPLS RD1/SEG1/T5CKI/T7G 55 RD1 SEG1 T5CKI T7G RD2/SEG2 54 RD2 SEG2 RD3/SEG3 53 RD3 SEG3 RD4/SEG4/SDO2 52 RD4 SEG4 SDO2 RD5/SEG5/SDI2/SDA2 51 RD5 SEG5 SDI2 SDA2 RD6/SEG6/SCK2/SCL2 50 RD6 SEG6 ...
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... Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Pin Buffer Type Type PORTE is a bidirectional I/O port. ...
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... PIC18F87K90 FAMILY TABLE 1-3: PIC18F6XK90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name QFN/TQFP RF1/AN6/C2OUT/SEG19/ 17 CTDIN RF1 AN6 C2OUT SEG19 CTDIN RF2/AN7/C1OUT/SEG20 16 RF2 AN7 C1OUT SEG20 RF3/AN8/SEG21/C2INB/ 15 CTMUI RF3 AN8 SEG21 C2INB CTMUI RF4/AN9/SEG22/C2INA 14 RF4 AN9 SEG22 C2INA RF5/AN10/ REF SEG23/C1INB ...
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... Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Pin Buffer Type Type PORTG is a bidirectional I/O port. ...
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... PIC18F87K90 FAMILY TABLE 1-3: PIC18F6XK90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name QFN/TQFP V 9, 25, 41 26, 38 ENVREG DDCORE CAP V DDCORE V CAP Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power C™ C/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. ...
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... Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 4: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Pin Buffer Type Type PORTA is a bidirectional I/O port. ...
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... PIC18F87K90 FAMILY TABLE 1-4: PIC18F8XK90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RB0/INT0/SEG30/FLT0 58 RB0 INT0 SEG30 FLT0 RB1/INT1/SEG8 57 RB1 INT1 SEG8 RB2/INT2/SEG9/CTED1 56 RB2 INT2 SEG9 CTED1 RB3/INT3/SEG10/ 55 CTED2/ECCP2/P2A RB3 INT3 SEG10 CTED2 ECCP2 P2A RB4/KBI0/SEG11 54 RB4 KBI0 SEG11 RB5/KBI1/SEG29/T3CKI/ ...
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... Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 4: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Pin Buffer Type Type I/O TTL Digital I/O ...
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... PIC18F87K90 FAMILY TABLE 1-4: PIC18F8XK90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RC0/SOSCO/SCKLI 36 RC0 SOSCO SCKLI RC1/SOSCI/ECCP2/ 35 SEG32/P2A RC1 SOSCI (1) ECCP2 SEG32 P2A RC2/ECCP1/P1A/SEG13 43 RC2 ECCP1 P1A SEG13 RC3/SCK1/SCL1/SEG17 44 RC3 SCK1 SCL1 SEG17 RC4/SDI1/SDA1/SEG16 45 RC4 SDI1 SDA1 SEG16 RC5/SDO1/SEG12 ...
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... Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 4: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Pin Buffer Type Type PORTD is a bidirectional I/O port. ...
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... PIC18F87K90 FAMILY TABLE 1-4: PIC18F8XK90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RE0/LCDBIAS1/P2D 4 RE0 LCDBIAS1 P2D RE1/LCDBIAS2/P2C 3 RE1 LCDBIAS2 P2C RE2/LCDBIAS3/P2B/ 78 CCP10 RE2 LCDBIAS3 P2B (3) CCP10 RE3/COM0/P3C/CCP9/ 77 REFO RE3 COM0 P3C (4) CCP9 REFO RE4/COM1/P3B/CCP8 76 RE4 COM1 P3B (4) CCP8 RE5/COM2/P1C/CCP7 ...
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... Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 4: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Pin Buffer Type Type PORTF is a bidirectional I/O port. ...
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... PIC18F87K90 FAMILY TABLE 1-4: PIC18F8XK90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RG0/ECCP3/P3A 5 RG0 ECCP3 P3A RG1/TX2/CK2/AN19/ 6 C3OUT RG1 TX2 CK2 AN19 C3OUT RG2/RX2/DT2/AN18/ 7 C3INA RG2 RX2 DT2 AN18 C3INA RG3/CCP4/AN17/P3D/ 8 C3INB RG3 CCP4 AN17 P3D C3INB RG4/SEG26/RTCC/ 10 T7CKI/T5G/CCP5/AN16/ ...
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... Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 4: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Pin Buffer Type Type PORTH is a bidirectional I/O port. ...
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... PIC18F87K90 FAMILY TABLE 1-4: PIC18F8XK90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RH7/SEG43/CCP6/P1B/ 19 AN15 RH7 SEG43 (4) CCP6 P1B AN15 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power C™ C/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. ...
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... Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K90 and PIC18F85K90 devices. 4: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Pin Buffer Type Type PORTJ is a bidirectional I/O port. ...
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... PIC18F87K90 FAMILY NOTES: DS39957B-page 34 Preliminary 2010 Microchip Technology Inc. ...
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... GUIDELINES FOR GETTING STARTED WITH PIC18FXXKXX MICROCONTROLLERS 2.1 Basic Connection Requirements Getting started with the PIC18F87K90 family family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: • All V ...
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... PIC18F87K90 FAMILY 2.2 Power Supply Pins 2.2.1 DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher ...
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... These devices also do not have the ENVREG pin. The 10F capacitor is still required on the V /V pin. CAP DDCORE For details on all members of the PIC18F87K90 family, see Section 28.3 “On-Chip Voltage Regulator”. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY FIGURE 2-3: 10 enables ...
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... PIC18F87K90 FAMILY 2.6 External Oscillator Pins Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator Section 3.0 “Oscillator Configurations” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0 ...
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... OSCILLATOR CONFIGURATIONS 3.1 Oscillator Types The PIC18F87K90 family of devices can be operated in the following oscillator modes: • EC External Clock, RA6 available • ECIO External Clock, Clock Out RA6 ( RA6) OSC • HS High-Speed Crystal/Resonator • XT Crystal/Resonator • LP Low-Power Crystal • RC External Resistor/Capacitor, RA6 available • ...
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... EC1IO) EC2 (medium power) (EC2 & EC2IO) EC3 (high power) (EC3 & EC3IO) HS1 (medium power) HS2 (high power (External) INTIO FIGURE 3-1: PIC18F87K90 FAMILY CLOCK DIAGRAM SOSCO SOSCI OSC2 OSC1 HF INTOSC 16 MHz to 31 kHz MF INTOSC 500 kHz to 31 kHz LF INTOSC ...
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... Modifying these bits will cause an immediate clock source switch. 5: INTSRC = OSCTUNE<7> and MFIOSEL = OSCCON2<0>. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY The OSCTUNE register (Register 3-3) controls the tuning and operation of the internal oscillator block. It also implements the PLLEN bit which controls the operation of the Phase Locked Loop (PLL) (see Section 3.5.2 “ ...
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... PIC18F87K90 FAMILY REGISTER 3-1: OSCCON: OSCILLATOR CONTROL REGISTER bit 2 HFIOFS: INTOSC Frequency Stable bit 1 = HF-INTOSC oscillator frequency is stable 0 = HF-INTOSC oscillator frequency is not stable bit 1-0 SCS<1:0>: System Clock Select bits 1x = Internal oscillator block (LF-INTOSC, MF-INTOSC or HF-INTOSC SOSC oscillator 00 = Default primary oscillator (OSC1/OSC2 or HF-INTOSC with or without PLL. Defined by the OSC< ...
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... Monitor. The internal oscillator block is discussed in more detail in Section 3.6 “Internal Oscillator Block”. The PIC18F87K90 family includes features that allow the device clock source to be switched from the main oscillator, chosen by device configuration, to one of the alternate clock sources. When an alternate clock source is enabled, various power-managed operating modes are available ...
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... SCS<1:0> bits, at any given time. SOSCRUN 3.3.3 OSCILLATOR TRANSITIONS PIC18F87K90 family devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs dur- ing the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source ...
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... Microchip Technology Inc. PIC18F87K90 FAMILY Note 1: Higher capacitance increases the stability of oscillator but also increases the start-up time. 2: Since each resonator/crystal has its own OSC2 characteristics, the user should consult the resonator/crystal manufacturer for ...
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... PIC18F87K90 FAMILY In the RC Oscillator mode, the oscillator frequency divided available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 3-3 shows how the R/C combination is connected. FIGURE 3-3: RC OSCILLATOR MODE EXT OSC1 C EXT PIC18FXXXX V SS ...
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... PLL is enabled only if the HF-INTOSC postscaler is configured for 4 MHz, 8 MHz or 16 MHz 3.6 Internal Oscillator Block The PIC18F87K90 family of devices includes an internal oscillator block which generates two different clock signals. Either clock can be used as the micro- controller’s clock source, which may eliminate the need for an external oscillator circuit on the OSC1 and/or OSC2 pins ...
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... PIC18F87K90 FAMILY 3.6.2 INTPLL MODES The 4x Phase Locked Loop (PLL) can be used with the HF-INTOSC to produce faster device clock speeds than are normally possible with the internal oscillator sources. When enabled, the PLL produces a clock speed of 16 MHz or 64 MHz. PLL operation is controlled through software. The con- trol bits, PLLEN (OSCTUNE< ...
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... Reference Clock Output In addition to the F /4 clock output in certain oscilla- OSC tor modes, the device clock in the PIC18F87K90 family can also be configured to provide a reference clock out- put signal to a port pin. This feature is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application ...
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... MSSP slave, INTx pins and others). Peripherals that may add significant current consumption are listed in Section 31.2 “DC Characteristics: Power-Down and Supply Current PIC18F87K90 Family (Industrial)”. 3.9 Power-up Delays and Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applica- tions ...
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... POWER-MANAGED MODES The PIC18F87K90 family of devices offers a total of seven operating modes for more efficient power man- agement. These modes provide a variety of options for selective power conservation in applications where resources may be limited (such as battery-powered devices). There are three categories of power-managed modes: • ...
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... PIC18F87K90 FAMILY 4.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. The HF- INTOSC and MF-INTOSC are termed as INTOSC in this chapter ...
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... HF-INTOSC) – there are no distinguishable differences between the PRI_RUN and RC_RUN modes during execution. Entering or exiting RC_RUN mode, however, causes a clock switch delay. Therefore, if the primary clock source is the internal oscillator block, using RC_RUN mode is not recommended. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY n-1 n (1) ...
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... PIC18F87K90 FAMILY If the IRCF bits and the INTSRC bit are all clear, the INTOSC output (HF-INTOSC/MF-INTOSC) is not enabled and the HFIOFS and MFIOFS bits will remain clear. There will be no indication of the current clock source. The LF-INTOSC source is providing the device clocks ...
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... Output CPU Clock Peripheral Clock Program Counter SCS<1:0> bits Changed Note1 1024 (approx). These intervals are not shown to scale. OST OSC PLL 2: Clock transition typically occurs within 2-4 T 2010 Microchip Technology Inc. PIC18F87K90 FAMILY n-1 n (1) Clock Transition OSC (1) (1) ...
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... PIC18F87K90 FAMILY 4.3 Sleep Mode The power-managed Sleep mode in the PIC18F87K90 family of devices is identical to the legacy Sleep mode offered in all other PIC devices entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 4-5) ...
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... Peripheral Clock Program Counter Wake Event 2010 Microchip Technology Inc. PIC18F87K90 FAMILY 4.4.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the SOSC oscillator. This mode is entered from SEC_RUN by set- ting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set the IDLEN bit first, then set the SCS< ...
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... Many peripheral modules have a corresponding PMD bit. There are four PMD registers in PIC18F87K90 family devices: PMD0, PMD1, PMD2 and PMD3. These registers have bits associated with each module for disabling or enabling a particular peripheral ...
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... TMR12MD: TMR12MD Disable bit 1 = PMD is enabled and all TMR12MD clock sources are disabled 0 = PMD is disabled and TMR12MD is enabled Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K90). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-0 R/W-0 CCP7MD CCP6MD CCP5MD U = Unimplemented bit, read as ‘ ...
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... PIC18F87K90 FAMILY REGISTER 4-2: PMD2: PERIPHERAL MODULE DISABLE REGISTER 2 R/W-0 R/W-0 R/W-0 (1) TMR10MD TMR8MD TMR7MD bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 TMR10MD: TMR10MD Disable bit 1 = Peripheral Module Disable (PMD) is enabled and all TMR10MD clock sources are disabled ...
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... Unimplemented: Read as ‘0’ Note 1: RTCCMD can only be set to ‘1’ after an EECON2 unlock sequence; refer to Section 17.0 “Real-Time Clock and Calendar (RTCC)” for the unlock sequence (see Example 17-1). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-0 R/W-0 (1) ...
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... PIC18F87K90 FAMILY REGISTER 4-4: PMD0: PERIPHERAL MODULE DISABLE REGISTER 0 R/W-0 R/W-0 R/W-0 CCP3MD CCP2MD CCP1MD bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 CCP3MD: PMD ECCP3 Enable/Disable bit 1 = Peripheral Module Disable (PMD) is enabled for ECCP3, disabling all of its clock sources ...
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... Fail-Safe Clock Monitor is enabled) and modifies the IRCF bits in the OSCCON register (if the internal oscillator block is the device clock source). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY 4.6.3 EXIT BY RESET Normally, the device is held in Reset by the Oscillator Start-up Timer (OST) until the primary clock becomes ready ...
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... PIC18F87K90 FAMILY 4.7 Ultra Low-Power Wake-up The Ultra Low-Power Wake-up (ULPWU) on pin, RA0, allows a slow falling voltage to generate an interrupt without excess current consumption. To use this feature: 1. Charge the capacitor on RA0 by configuring the RA0 pin to an output and setting it to ‘1’. ...
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... OST (parameter F12, Table 31-7 also designated Execution continues during T 5: The clock source is dependent upon the settings of the SCS (OSCCON<1:0>), IRCF (OSCCON<6:4>) and FOSC (CONFIG1H<3:0>) bits. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY (5) Clock Source Exit Delay LP, XT, HS HSPLL EC CSD ...
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... PIC18F87K90 FAMILY NOTES: DS39957B-page 66 Preliminary 2010 Microchip Technology Inc. ...
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... RESET The PIC18F87K90 family of devices differentiates between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset (during execution) e) Configuration Mismatch (CM) Reset f) Brown-out Reset (BOR) g) RESET Instruction h) Stack Full Reset ...
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... PIC18F87K90 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-1 R/W-1 IPEN SBOREN CM bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) ...
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... To capture multiple events, the user manually resets the bit to ‘1’ in software following any Power-on Reset. 5.4 Brown-out Reset (BOR) The PIC18F87K90 family has four BOR modes: • High-Power BOR • Medium Power BOR • Low-Power BOR • Zero-Power BOR Each power mode is selected by the BORPWR< ...
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... PWRTEN bit (CONFIG2L<0>). The main function is to ensure that the device voltage is stable before code is executed. The Power-up Timer (PWRT) of the PIC18F87K90 family devices is a 13-bit counter that uses the LF-INTOSC source as the clock input. This yields an approximate time interval of 2,048 x 32 ms. ...
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... TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET 2010 Microchip Technology Inc. PIC18F87K90 FAMILY T PWRT T PWRT , V RISE > 3. PWRT Preliminary ): CASE 1 ...
Page 72
... PIC18F87K90 FAMILY 5.7 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation ...
Page 73
... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for Reset value for specific condition. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, Brown-out Reset Stack Resets, ...
Page 74
... PIC18F87K90 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices INDF2 PIC18F6XK90 PIC18F8XK90 POSTINC2 PIC18F6XK90 PIC18F8XK90 POSTDEC2 PIC18F6XK90 PIC18F8XK90 PREINC2 PIC18F6XK90 PIC18F8XK90 PLUSW2 PIC18F6XK90 PIC18F8XK90 FSR2H PIC18F6XK90 PIC18F8XK90 FSR2L PIC18F6XK90 PIC18F8XK90 STATUS PIC18F6XK90 PIC18F8XK90 TMR0H PIC18F6XK90 PIC18F8XK90 TMR0L ...
Page 75
... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for Reset value for specific condition. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, Brown-out Reset Stack Resets, ...
Page 76
... PIC18F87K90 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices PSTR1CON PIC18F6XK90 PIC18F8XK90 OSCTUNE PIC18F6XK90 PIC18F8XK90 TRISJ PIC18F6XK90 PIC18F8XK90 TRISH PIC18F6XK90 PIC18F8XK90 TRISG PIC18F6XK90 PIC18F8XK90 TRISF PIC18F6XK90 PIC18F8XK90 TRISE PIC18F6XK90 PIC18F8XK90 TRISD PIC18F6XK90 PIC18F8XK90 TRISC PIC18F6XK90 PIC18F8XK90 TRISB ...
Page 77
... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for Reset value for specific condition. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, Brown-out Reset Stack Resets, ...
Page 78
... PIC18F87K90 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices EEADR PIC18F6XK90 PIC18F8XK90 EEDATA PIC18F6XK90 PIC18F8XK90 PIE6 PIC18F6XK90 PIC18F8XK90 RTCCFG PIC18F6XK90 PIC18F8XK90 RTCCAL PIC18F6XK90 PIC18F8XK90 RTCVALH PIC18F6XK90 PIC18F8XK90 RTCVALL PIC18F6XK90 PIC18F8XK90 ALRMCFG PIC18F6XK90 PIC18F8XK90 ALRMRPT PIC18F6XK90 PIC18F8XK90 ALRMVALH ...
Page 79
... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for Reset value for specific condition. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, Brown-out Reset Stack Resets, ...
Page 80
... PIC18F87K90 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices SPBRGH2 PIC18F6XK90 PIC18F8XK90 SPBRG2 PIC18F6XK90 PIC18F8XK90 RCREG2 PIC18F6XK90 PIC18F8XK90 TXREG2 PIC18F6XK90 PIC18F8XK90 PSTR2CON PIC18F6XK90 PIC18F8XK90 PSTR3CON PIC18F6XK90 PIC18F8XK90 PMD0 PIC18F6XK90 PIC18F8XK90 PMD1 PIC18F6XK90 PIC18F8XK90 PMD2 PIC18F6XK90 PIC18F8XK90 PMD3 ...
Page 81
... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for Reset value for specific condition. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, Brown-out Reset Stack Resets, ...
Page 82
... PIC18F87K90 FAMILY NOTES: DS39957B-page 82 Preliminary 2010 Microchip Technology Inc. ...
Page 83
... MEMORY ORGANIZATION PIC18F87K90 family devices have these types of memory: • Program Memory • Data RAM • Data EEPROM As Harvard architecture devices, the data and program memories use separate busses. concurrent access of the two memory spaces. FIGURE 6-1: MEMORY MAPS FOR PIC18F87K90 FAMILY DEVICES ...
Page 84
... Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘0’s (a NOP instruction). The entire PIC18F87K90 family offers a range of on-chip Flash program memory sizes, from 32 Kbytes (up to 16,384 single-word instructions) to 128 Kbytes (65,536 single-word instructions). ...
Page 85
... Microchip Technology Inc. PIC18F87K90 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers ...
Page 86
... PIC18F87K90 FAMILY 6.1.3.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 6-1) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack ...
Page 87
... SUB1 RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK 2010 Microchip Technology Inc. PIC18F87K90 FAMILY 6.1.5 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
Page 88
... PIC18F87K90 FAMILY 6.2 PIC18 Instruction Cycle 6.2.1 CLOCKING SCHEME The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the program counter is incremented on every Q1, with the instruction fetched from the program memory and latched into the Instruction Register (IR) during Q4 ...
Page 89
... ADDWF 2010 Microchip Technology Inc. PIC18F87K90 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...
Page 90
... PIC18F87K90 FAMILY 6.3 Data Memory Organization Note: The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 6.6 “Data Memory and the Extended Instruction Set” for more information. The data memory in PIC18 devices is implemented as static RAM ...
Page 91
... BSR value, to access these registers. 2: These addresses are unused for devices with 32 Kbytes of program memory (PIC18FX5K90). For those devices, read these addresses at 00h. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Data Memory Map 000h Access RAM ...
Page 92
... PIC18F87K90 FAMILY FIGURE 6-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) (1) BSR (2) Bank Select Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. ...
Page 93
... RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy all of Bank 15 (F00h to FFFh) and the top part of Bank 14 (EF4h to EFFh). A list of these registers is given in Table 6-1 and Table 6-2. TABLE 6-1: PIC18F87K90 FAMILY SPECIAL FUNCTION REGISTER MAP Name Name Addr. Addr. (1) FFFh ...
Page 94
... PIC18F87K90 FAMILY TABLE 6-1: PIC18F87K90 FAMILY SPECIAL FUNCTION REGISTER MAP Name Name Addr. Addr. (4) (4) F3Fh TMR7H F32h TMR12 (4) (4) F3Eh TMR7L F31h PR12 (4) (4) F3Dh T7CON F30h T12CON (4) F3Ch T7GCON F2Fh CM2CON F3Bh F2Eh TMR6 CM3CON F3Ah F2Dh CCPTMRS0 PR6 ...
Page 95
... TABLE 6-2: PIC18F87K90 FAMILY REGISTER FILE SUMMARY Address File Name Bit 7 Bit 6 EF4h LCDCON LCDEN SLPEN EF5h LCDPS WFT BIASMD EF6h LCDSE0 SE07 SE06 EF7h LCDSE1 SE15 SE14 EF8h LCDSE2 SE23 SE22 EF9h LCDSE3 SE31 SE30 EFAh LCDSE4 SE39 SE38 (2) EFBh ...
Page 96
... PIC18F87K90 FAMILY TABLE 6-2: PIC18F87K90 FAMILY REGISTER FILE SUMMARY (CONTINUED) Address File Name Bit 7 Bit 6 F24h ANCON1 ANSEL15 ANSEL14 F25h ANCON0 ANSEL7 ANSEL6 — — — F27h ODCON3 U2OD U1OD F28h ODCON2 CCP10OD CCP9OD F29H ODCON1 SSP1OD CCP2OD F2Ah REFOCON ROON — ...
Page 97
... TABLE 6-2: PIC18F87K90 FAMILY REGISTER FILE SUMMARY (CONTINUED) Address File Name Bit 7 Bit 6 F50h CCPR2H Capture/Compare/PWM Register 2 High Byte F51h ECCP2DEL P2RSEN P2DC6 F52h ECCP2AS ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 F53h PADCFG1 RDPU REPU F54h CM1CON CON COE F55h CTMUICON ITRIM5 ITRIM4 ...
Page 98
... PIC18F87K90 FAMILY TABLE 6-2: PIC18F87K90 FAMILY REGISTER FILE SUMMARY (CONTINUED) Address File Name Bit 7 Bit 6 F81h PORTB RB7 RB6 F82h PORTC RC7 RC6 F83h PORTD RD7 RD6 F84h PORTE RE7 RE6 F85h PORTF RF7 RF6 F86h PORTG — — (2) F87h PORTH ...
Page 99
... TABLE 6-2: PIC18F87K90 FAMILY REGISTER FILE SUMMARY (CONTINUED) Address File Name Bit 7 Bit 6 FB0h T3GCON TMR3GE T3GPOL FB1h T3CON TMR3CS1 TMR3CS0 FB2h TMR3L Timer3 Register Low Byte FB3h TMR3H Timer3 Register High Byte FB4h CMSTAT CMP3OUT CMP2OUT FB5h CVRCON CVREN CVROE ...
Page 100
... PIC18F87K90 FAMILY TABLE 6-2: PIC18F87K90 FAMILY REGISTER FILE SUMMARY (CONTINUED) Address File Name Bit 7 Bit 6 FDFh INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) FE0h BSR — — FE1h FSR1L Indirect Data Memory Address Pointer 1 Low Byte ...
Page 101
... For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY It is recommended, therefore, that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions be used to alter the STATUS register because these instructions do not affect the bits in the STATUS register ...
Page 102
... PIC18F87K90 FAMILY 6.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. For more information, Section 6.6 “Data Memory and the Extended Instruction Set”. While the program memory can be addressed in only ...
Page 103
... FCCh, will be added to that of the W register and stored back in FCCh. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY are mapped in the SFR space, but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L ...
Page 104
... PIC18F87K90 FAMILY 6.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value ...
Page 105
... Address Pointer specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY 6.6.2 INSTRUCTIONS AFFECTED BY INDEXED LITERAL OFFSET MODE Any of the core PIC18 instructions that can use Direct Addressing are potentially affected by the Indexed Literal Offset Addressing mode ...
Page 106
... PIC18F87K90 FAMILY FIGURE 6-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF (Opcode: 0010 01da ffff ffff) When and f 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and FFFh ...
Page 107
... F00h BSR. F60h FFFh 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Remapping the Access Bank applies only to operations using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit = 1) will continue to use Direct Addressing as before. Any Indirect or Indexed ...
Page 108
... PIC18F87K90 FAMILY NOTES: DS39957B-page 108 Preliminary 2010 Microchip Technology Inc. ...
Page 109
... Program Memory (TBLPTR) Note 1: The Table Pointer register points to a byte in program memory. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY 7.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
Page 110
... PIC18F87K90 FAMILY FIGURE 7-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: The Table Pointer actually points to one of 64 holding registers; the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 7.5 “ ...
Page 111
... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-x R/W-0 (1) FREE ...
Page 112
... PIC18F87K90 FAMILY 7.2.2 TABLAT – TABLE LATCH REGISTER The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 7.2.3 TBLPTR – TABLE POINTER ...
Page 113
... MOVF TABLAT, W MOVF WORD_ODD 2010 Microchip Technology Inc. PIC18F87K90 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
Page 114
... PIC18F87K90 FAMILY 7.4 Erasing Flash Program Memory The erase block is 32 words or 64 bytes for the PIC18FX5K90 and PIC18FX6K90 64 words or 128 bytes for the PIC18FX7K90 devices. Word erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block 128 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR< ...
Page 115
... Set WREN to enable byte writes 8. Disable the interrupts. 9. Write 0x55 to EECON2. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY The long write is necessary for programming the inter- nal Flash. Instruction execution is halted while in a long write cycle. The long write is terminated by the internal devices, and programming timer ...
Page 116
... PIC18F87K90 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW SIZE_OF_BLOCK MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ MOVF TABLAT, W MOVWF POSTINC0 DECFSZ COUNTER BRA ...
Page 117
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: Bit 21 of TBLPTRU allows access to the device Configuration bits. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY ; point to Flash program memory ; access Flash program memory ; enable write to memory ...
Page 118
... PIC18F87K90 FAMILY NOTES: DS39957B-page 118 Preliminary 2010 Microchip Technology Inc. ...
Page 119
... The data EEPROM is a nonvolatile memory array, separate from the data RAM and program memory, that is used for long-term storage of program data. The PIC18F87K90 family of devices has a 1024-byte data EEPROM not directly mapped in either the register file or program memory space, but is indirectly addressed through the Special Function Registers (SFRs) ...
Page 120
... PIC18F87K90 FAMILY REGISTER 8-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 EEPGD CFGS — bit 7 Legend Settable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory ...
Page 121
... INTCON, GIE BCF EECON1, WREN 2010 Microchip Technology Inc. PIC18F87K90 FAMILY execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware. After a write sequence has been initiated, EECON1, EEADRH:EEADR and EEDATA cannot be modified ...
Page 122
... PIC18F87K90 FAMILY 8.6 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in Configuration Words. External read operations are disabled if code protection is enabled. The microcontroller itself can both read and write to the internal data EEPROM regardless of the state of the code-protect Configuration bit. Refer to Section 28.0 “ ...
Page 123
... EEPROM Data Register EECON2 EEPROM Control Register 2 (not a physical register) EECON1 EEPGD CFGS Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — ...
Page 124
... PIC18F87K90 FAMILY NOTES: DS39957B-page 124 Preliminary 2010 Microchip Technology Inc. ...
Page 125
... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply 2010 Microchip Technology Inc. PIC18F87K90 FAMILY EXAMPLE 9-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 9-2: MOVF ARG1, W MULWF ARG2 BTFSC ARG2, SB ...
Page 126
... PIC18F87K90 FAMILY Example 9-3 shows the sequence unsigned multiplication. Equation 9-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 9- UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L ARG2H:ARG2L RES3:RES0 = 16 (ARG1H ARG2H (ARG1H ARG2L (ARG1L ARG2H 2 (ARG1L ...
Page 127
... INTERRUPTS Members of the PIC18F87K90 family of devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress ...
Page 128
... PIC18F87K90 FAMILY FIGURE 10-1: PIC18F87K90 FAMILY INTERRUPT LOGIC PIR1<6:0> PIE1<6:0> IPR1<6:0> PIR2<7,5:0> PIE2<7,5:0> IPR2<7:7,5:0> PIR3<6:0> PIE3<6:0> IPR3<6:0> PIR3<7:0> PIE3<7:0> IPR3<7:0> PIR5<7:0> PIE5<7:0> IPR5<7:0> PIR6<4,2:0> PIE6<4,2:0> IPR6<4,2:0> High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<6:0> PIE1<6:0> IPR1<6:0> PIR2<7,5:0> PIE2<7,5:0> IPR2<7,5:0> PIR3<7:0> PIE3<7:0> IPR3<7:0> ...
Page 129
... A mismatch condition will continue to set this bit. Reading PORTB, and then waiting one additional instruction cycle, will end the mismatch condition and allow the bit to be cleared. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Note: Interrupt flag bits are set when an interrupt ...
Page 130
... PIC18F87K90 FAMILY REGISTER 10-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values ...
Page 131
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-0 R/W-0 ...
Page 132
... PIC18F87K90 FAMILY 10.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are six Peripheral Interrupt Request (Flag) registers (PIR1 through PIR6). REGISTER 10-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 ...
Page 133
... TMR3 register overflowed (must be cleared in software TMR3 register did not overflow bit 0 TMR3GIF: TMR3 Gate Interrupt Flag bit 1 = Timer gate interrupt occurred (must be cleared in software timer gate interrupt occurred 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-0 R/W-0 BCL2IF BCL1IF HLVDIF U = Unimplemented bit, read as ‘ ...
Page 134
... PIC18F87K90 FAMILY REGISTER 10-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 R-0 TMR5GIF LCDIF RC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 TMR5GIF: Timer5 Gate Interrupt Flag bit 1 = Timer gate interrupt occured (must be cleared in software) ...
Page 135
... A TMR register compare match occurred (must be cleared in software TMR register compare match occurred PWM Mode Not used in PWM mode. Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K90). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-0 R/W-0 CCP7IF CCP6IF CCP5IF U = Unimplemented bit, read as ‘ ...
Page 136
... PIC18F87K90 FAMILY REGISTER 10-8: PIR5: PERIPHERAL INTERRUPT FLAG REGISTER 5 R/W-0 R/W-0 R/W-0 (1) (1) TMR7GIF TMR12IF TMR10IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 TMR7GIF: TMR7 Gate Interrupt Flag bits 1 = TMR gate interrupt occurred (must be cleared in software) ...
Page 137
... CMP2 interrupt occurred (must be cleared in software CMP2 interrupt occurred bit 0 CMP1IF: CM1 Interrupt Flag bit 1 = CMP1 interrupt occurred (must be cleared in software CMP1 interrupt occurred 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 U-0 R/W-0 EEIF — CMP3IF U = Unimplemented bit, read as ‘0’ ...
Page 138
... PIC18F87K90 FAMILY 10.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are six Peripheral Interrupt Enable registers (PIE1 through PIE6). When IPEN (RCON<7> the PEIE bit must be set to enable any of these peripheral interrupts ...
Page 139
... TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 TMR3GIE: Timer3 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-0 R/W-0 BCL2IE BCL1IE HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary ...
Page 140
... PIC18F87K90 FAMILY REGISTER 10-12: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0 R/W-0 R-0 TMR5GIE LCDIE RC2IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 TMR5GIE: Timer5 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 LCDIE: LCD Interrupt Enable bit ...
Page 141
... TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enables the TMR4 to PR4 match interrupt 0 = Disables the TMR4 to PR4 match interrupt Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K90). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-0 R/W-0 (1) (1) TMR8IE ...
Page 142
... PIC18F87K90 FAMILY REGISTER 10-15: PIE6: PERIPHERAL INTERRUPT ENABLE REGISTER 6 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4 EEIE: Data EEDATA/Flash Write Operation Enable bit ...
Page 143
... TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-1 R/W-1 R/W-1 TX1IP SSP1IP TMR1GIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 144
... PIC18F87K90 FAMILY REGISTER 10-17: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 U-0 R/W-1 OSCFIP — SSP2IP bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 Unimplemented: Read as ‘0’ ...
Page 145
... CCP10IP:CCP3IP: CCP<10:3> Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: CCP10IP and CCP9IP are unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K90). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R-1 R/W-1 R/W-1 TX2IP CTMUIP CCP2IP U = Unimplemented bit, read as ‘0’ ...
Page 146
... PIC18F87K90 FAMILY REGISTER 10-20: IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5 R/W-1 R/W-1 R/W-1 (1) (1) TMR7GIP TMR12IP TMR10IP bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 TMR7GIP: TMR7 Gate Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 TMR12IP: TMR12 to PR12 Match Interrupt Priority bit ...
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... CMP2IP: CMP2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CMP1IP: CMP1 Interrupt Priority bit 1 = High priority 0 = Low priority 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-1 U-0 R/W-1 EEIE — CMP3IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... PIC18F87K90 FAMILY 10.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the bit that enables interrupt priorities (IPEN). REGISTER 10-22: RCON: RESET CONTROL REGISTER R/W-0 R/W-1 R/W-1 ...
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... MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS 2010 Microchip Technology Inc. PIC18F87K90 FAMILY The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON<5>). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit, TMR0IP (INTCON2<2>). For further details on the Timer0 module, see Section 12.0 “Timer0 Module” ...
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... PIC18F87K90 FAMILY TABLE 10-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL INTCON2 RBPU INTEDG0 INTCON3 INT2IP INT1IP PIR1 — ADIF PIR2 OSCFIF — PIR3 TMR5GIF LCDIF (1) (1) PIR4 CCP10IF CCP9IF (1) (1) PIR5 TMR7GIF TMR12IF PIR6 — — ...
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... RD TRIS PORT 2010 Microchip Technology Inc. PIC18F87K90 FAMILY 11.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V All of the digital ports are 5 ...
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... PIC18F87K90 FAMILY 11.1.3 OPEN-DRAIN OUTPUTS The output pins for several peripherals are also equipped with a configurable, open-drain output option. This allows the peripherals to communicate with external digital logic, operating at a higher voltage level, without the use of level translators. The open-drain option is implemented on port pins ...
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... Open-drain capability is disabled bit 0 CCP3OD: ECCP3 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled Note 1: Unimplemented on PIC18FX5K90 devices. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-0 R/W-0 CCP7OD CCP6OD CCP5OD U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... ANALOG AND DIGITAL PORTS Many of the ports multiplex analog and digital function- ality, providing a lot of flexibility for hardware designers. PIC18F87K90 family devices can make any analog pin analog or digital, depending on an application’s needs. The ports’ analog/digital functionality is controlled by the registers: ANCON0, ANCON1 and ANCON2. ...
Page 155
... RA5 and RA<3:0> are configured as analog inputs on any Reset and are read as ‘0’. RA4 is configured as a digital input. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY OSC2/CLKO/RA6 and serve as the external circuit connections for the exter- nal (primary) oscillator circuit (HS Oscillator modes) or the external clock input and output (EC Oscillator modes) ...
Page 156
... PIC18F87K90 FAMILY TABLE 11-1: PORTA FUNCTIONS TRIS Pin Name Function Setting RA0/AN0/ULPWU RA0 0 1 AN0 1 ULPWU 1 RA1/AN1/SEG18 RA1 0 1 AN1 1 SEG18 1 RA2/AN2/V - RA2 REF 0 1 AN2 REF 1 RA3/AN3/V + RA3 REF 0 1 AN3 REF 1 RA4/T0CKI/ RA4 0 SEG14 1 T0CKI x SEG14 1 RA5/AN4/SEG15/ RA5 0 T1CKI/T3G/ ...
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... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘x’. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 ...
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... PIC18F87K90 FAMILY 11.3 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISB and LATB. All pins on PORTB are digital only. EXAMPLE 11-2: INITIALIZING PORTB CLRF PORTB ; Initialize PORTB by ; clearing output ...
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... O = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY I/O I/O Type ...
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... PIC18F87K90 FAMILY TABLE 11-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 PORTB RB7 RB6 LATB LATB7 LATB6 TRISB TRISB7 TRISB6 TRISB5 INTCON GIE/GIEH PEIE/GIEL TMR0IE INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 INTCON3 INT2IP INT1IP LCDSE1 SE15 SE14 LCDSE3 SE31 SE30 Legend: Shaded cells are not used by PORTB ...
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... Note: These pins are configured as digital inputs on any device Reset. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins. ...
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... PIC18F87K90 FAMILY TABLE 11-5: PORTC FUNCTIONS TRIS Pin Name Function I/O Setting RC0/SOSCO/ RC0 O 0 SCLKI SOSCO I 1 SCLKI O x RC1/SOSCI/ RC1 O 0 ECCP2/P2A SEG32 SOSCI I x (1) ECCP2 P2A O 0 SEG32 O 1 RC2/ECCP1/ RC2 O 0 P1A/SEG13 I 1 ECCP1 P1A O 0 SEG13 ...
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... SE38 ODCON1 SSP1OD CCP2OD CCP1OD Legend: Shaded cells are not used by PORTC. Note 1: Unimplemented on PIC18F6XK90 devices, read as ‘0’. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY I/O Type DIG LATC<7> data output. ST PORTC<7> data input. ST Asynchronous serial receive data input (EUSART module). ...
Page 164
... PIC18F87K90 FAMILY 11.5 PORTD, TRISD and LATD Registers PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISD and LATD. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. ...
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... O = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY I/O I/O Type O DIG LATD<0> data output PORTD< ...
Page 166
... PIC18F87K90 FAMILY TABLE 11-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Name Bit 7 Bit 6 Bit 5 PORTD RD7 RD6 RD5 LATD LATD7 LATD6 LATD5 TRISD TRISD7 TRISD6 TRISD5 LCDSE0 SE07 SE06 SE05 PADCFG1 RDPU REPU RJPU Legend: Shaded cells are not used by PORTD. Note 1: Not available on 64-pin devices ...
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... LCDBIASx pins are also available as I/O ports (RE0, RE1 and RE2). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Pins, RE2, RE1 and RE0, are multiplexed with the functions of LCDBIAS3, LCDBIAS2 and LCDBIAS1. When LCD bias generation is required (in any applica- tion where the device is connected to an external LCD), these pins cannot be used as digital I/O ...
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... PIC18F87K90 FAMILY TABLE 11-10: PORTE FUNCTIONS TRIS Pin Name Function Setting RE0/LCDBIAS1/ RE0 0 P2D 1 LCDBIAS1 — P2D 0 RE1/LCDBIAS2/ RE1 0 P2C 1 LCDBIAS2 — P2C 0 RE2/LCDBIAS3/ RE2 0 P2B 1 LCDBIAS3 x P2B 0 RE3/COM0/ RE3 0 P3C/CCP9/ 1 REFO COM0 x P3C 0 CCP9 0 1 REFO x RE4/COM1/ RE4 0 P3B/CCP8 1 COM1 ...
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... CCP2OD CCP1OD ODCON2 CCP10OD CCP9OD CCP8OD CCP7OD CCP6OD PADCFG1 RDPU REPU RJPU Legend: Shaded cells are not used by PORTE. Note 1: Not available on 64-pin devices. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY I/O I/O Type O DIG LATE<7> data output PORTE<7> data input. O DIG ECCP2 compare/PWM output ...
Page 170
... PIC18F87K90 FAMILY 11.7 PORTF, LATF and TRISF Registers PORTF is a 7-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISF and LATF. All pins on PORTF are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. ...
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... O = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY I/O I/O Type ...
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... PIC18F87K90 FAMILY TABLE 11-13: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Name Bit 7 Bit 6 PORTF RF7 RF6 LATF LATF7 LATF6 TRISF TRISF7 TRISF6 ANCON0 ANSEL7 ANSEL6 ANCON1 ANSEL15 ANSEL14 ANSEL13 ANSEL12 ANSEL11 ANSEL10 ANSEL9 CMSTAT CMP3OUT CMP2OUT CMP1OUT CVRCON CVREN CVROE LCDSE2 SE23 ...
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... O = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). 2010 Microchip Technology Inc. PIC18F87K90 FAMILY When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTG pin. Some ...
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... PIC18F87K90 FAMILY TABLE 11-14: PORTG FUNCTIONS (CONTINUED) TRIS Pin Name Function Setting RG2/RX2/DT2/ RG2 0 AN18/C3INA 1 RX2 1 DT2 1 1 AN18 1 C3INA x RG3/CCP4/AN17/ RG3 0 P3D/C3INB 1 CCP4 0 1 AN17 1 C3INB x P3D 0 RG4/SEG26/ RG4 0 RTCC/T7CKI/ 1 T5G/CCP5/ SEG26 1 AN16/P1D/ RTCC C3INC x T7CKI x T5G x CCP5 0 1 AN16 ...
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... ADC/CCP/Comparator and LCD segment controlled by the LCDSE5 register. I/O port functions are only available when the segments are disabled. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY EXAMPLE 11-8: CLRF PORTH CLRF LATH BANKSEL ANCON2 MOVLW 0Fh MOVWF ANCON2 ...
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... PIC18F87K90 FAMILY TABLE 11-16: PORTH FUNCTIONS TRIS Pin Name Function Setting RH0/SEG47/ RH0 0 AN23 1 SEG47 1 AN23 1 RH1/SEG46/ RH1 0 AN22 1 SEG46 1 AN22 1 RH2/SEG45/ RH2 0 AN21 1 SEG45 1 AN21 1 RH3/SEG44/ RH3 0 AN20 1 SEG44 1 AN20 1 RH4/SEG40/ RH4 0 CCP9/P3C/ 1 AN12/C2INC SEG40 1 CCP9 0 1 P3C 0 AN12 1 C2INC ...
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... SE46 ANCON1 ANSEL15 ANSEL14 ANSEL13 ANSEL12 ANSEL11 ANSEL10 ANSEL9 ANCON2 ANSEL23 ANSEL22 ANSEL21 ANSEL20 ANSEL19 ANSEL18 ANSEL17 ANSEL16 ODCON2 CCP10OD CCP9OD CCP8OD CCP7OD CCP6OD CCP5OD CCP4OD CCP3OD 2010 Microchip Technology Inc. PIC18F87K90 FAMILY I/O I/O Type O DIG LATH<6> data output PORTH< ...
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... PIC18F87K90 FAMILY 11.10 PORTJ, TRISJ and LATJ Registers Note: PORTJ is available only on 80-pin devices. PORTJ is an 8-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISJ and LATJ. All pins on PORTJ are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output ...
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... SE39 SE38 SE37 PADCFG1 RDPU REPU RJPU Legend: Shaded cells are not used by PORTJ. Note 1: Unimplemented on PIC18F6XK90 devices, read as ‘0’. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY I/O I/O Type DIG LATJ<0> data output PORTJ<0> data input. I DIG LATJ<1> data output. ...
Page 180
... PIC18F87K90 FAMILY NOTES: DS39957B-page 180 Preliminary 2010 Microchip Technology Inc. ...
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... Prescale value 000 = 1:2 Prescale value 2010 Microchip Technology Inc. PIC18F87K90 FAMILY The T0CON register (Register 12-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. Figure 12-1 provides a simplified block diagram of the Timer0 module in 8-bit mode ...
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... PIC18F87K90 FAMILY 12.1 Timer0 Operation Timer0 can operate as either a timer or a counter. The mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 12.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles ...
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... GIE/GIEH PEIE/GIEL TMR0IE T0CON TMR0ON T08BIT Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY 12.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution ...
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... PIC18F87K90 FAMILY NOTES: DS39957B-page 184 Preliminary 2010 Microchip Technology Inc. ...
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... The F clock source should not be selected if the timer will be used with the ECCP capture/compare features. OSC 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Figure 13-1 displays a simplified block diagram of the Timer1 module. The SOSC oscillator can also be used as a low-power clock source for the microcontroller in power-managed operation ...
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... PIC18F87K90 FAMILY 13.1 Timer1 Gate Control Register The Timer1 Gate Control register displayed in Register 13-2, is used to control the Timer1 gate. REGISTER 13-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0 R/W-0 R/W-0 TMR1GE T1GPOL T1GTM bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘ ...
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... Microchip Technology Inc. PIC18F87K90 FAMILY 13.3.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 module may work as a timer or a counter. When enabled to count, Timer1 is incremented on the rising edge of the external clock input, T1CKI. Either of these external clock sources can be synchronized to the ...
Page 188
... PIC18F87K90 FAMILY FIGURE 13-1: TIMER1 BLOCK DIAGRAM T1GSS<1:0> T1G 00 From Timer2 01 Match PR2 From Comp Output From Comp Output TMR1ON T1GPOL T1GTM Set Flag bit TMR1IF on Overflow TMR1 TMR1H SOSCO/T1CKI OUT T1OSC SOSCI EN SOSCEN (1) T1CKI Note 1: ST buffer is a high-speed type when using T1CKI. ...
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... SOSCI XTAL 32.768 kHz SOSCO Note: See the Notes with Table 13-2 for additional information about capacitor selection. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY TABLE 13-2: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Oscillator Freq. Type LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
Page 190
... PIC18F87K90 FAMILY 13.5.1 USING SOSC AS A CLOCK SOURCE The SOSC oscillator is also available as a clock source in power-managed modes. By setting the clock select bits, SCS<1:0> (OSCCON<1:0>), to ‘01’, the device switches to SEC_RUN mode and both the CPU and peripherals are clocked from the SOSC oscillator. If the IDLEN bit (OSCCON< ...
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... This is also referred to as Timer1 gate count enable. Timer1 gate can also be driven by multiple selectable sources. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY 13.8.1 TIMER1 GATE COUNT ENABLE The Timer1 Gate Enable mode is enabled by setting the TMR1GE bit of the T1GCON register. The polarity of the Timer1 Gate Enable mode is configured using the T1GPOL bit (T1GCON< ...
Page 192
... PIC18F87K90 FAMILY FIGURE 13-4: TIMER1 GATE COUNT ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N 13.8.2 TIMER1 GATE SOURCE SELECTION The Timer1 gate source can be selected from one of four sources. Source selection is controlled by the T1GSSx bits, T1GCON<1:0> (see Table 13-4). TABLE 13-4: TIMER1 GATE SOURCES T1GSS< ...
Page 193
... T1GVAL Timer1 2010 Microchip Technology Inc. PIC18F87K90 FAMILY The T1GVAL bit (T1GCON<2>) indicates when the Toggled mode is active and the timer is counting. The Timer1 Gate Toggle mode is enabled by setting the T1GTM bit (T1GCON<5>). When T1GTM is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured ...
Page 194
... PIC18F87K90 FAMILY 13.8.4 TIMER1 GATE SINGLE PULSE MODE When Timer1 Gate Single Pulse mode is enabled possible to capture a single pulse gate event. Timer1 Gate Single Pulse mode is enabled by setting the T1GSPM bit (T1GCON<4>) and the T1GGO/T1DONE bit (T1GCON<3>). The Timer1 will be fully enabled on the next incrementing edge ...
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... SOSCRUN CCPTMRS0 C3TSEL1 C3TSEL0 C2TSEL2 C2TSEL1 C2TSEL0 C1TSEL2 C1TSEL1 C1TSEL0 CCPTMRS1 C7TSEL1 C7TSEL0 CCPTMRS2 — — Legend: Shaded cells are not used by the Timer1 module. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY Set by Hardware on Falling Edge of T1GVAL Bit 5 Bit 4 Bit 3 ...
Page 196
... PIC18F87K90 FAMILY NOTES: DS39957B-page 196 Preliminary 2010 Microchip Technology Inc. ...
Page 197
... Prescaler Prescaler Prescaler is 16 2010 Microchip Technology Inc. PIC18F87K90 FAMILY The value of TMR2 is compared to that of the Period reg- ister, PR2, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMR2 to 00h on the next cycle and drives the output counter/ postscaler. (See Section 14.2 “ ...
Page 198
... PIC18F87K90 FAMILY 14.2 Timer2 Interrupt Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) pro- vides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag, which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1< ...
Page 199
... Timer7 module. For example, the control register is named TxCON and refers to T3CON, T5CON and T7CON. 2010 Microchip Technology Inc. PIC18F87K90 FAMILY A simplified block diagram of the Timer3/5/7 module is shown in Figure 15-1. The Timer3/5/7 module is controlled through the TxCON register (Register 15-1). It also selects the clock source options for the ECCP modules. (For more information, see Section 19.1.1 “ ...
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... PIC18F87K90 FAMILY REGISTER 15-1: TxCON: TIMERx CONTROL REGISTER R/W-0 R/W-0 R/W-0 TMRxCS1 TMRxCS0 TxCKPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 TMRxCS<1:0>: Timerx Clock Source Select bits 10 = The Timer1 clock source is either a pin or an oscillator depending on the SOSCEN bit. ...