DSPIC30F3011-30I/P Microchip Technology, DSPIC30F3011-30I/P Datasheet - Page 16

• Manufacturer Part Number: DSPIC30F3011-30I/P
• Description: IC DSPIC MCU/DSP 24K 40DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3011-30I/P

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 24KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F003 - MODULE SOCKET DSPIC30F 40DIPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLEACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F3011-30IP

dsPIC30F Family Reference Manual
35.3.3.1
DS70272B-page 35-16
Frame Master and Frame Slave Modes
The SPI1 module supports two framed modes of operation. In Framed Master mode, the SPI1
module generates the frame synchronization pulse and provides this pulse to other devices at
the SS1 pin. In Framed Slave mode, the SPI1 module uses a frame synchronization pulse
received at the SS1 pin.
The following four Framed SPI modes are supported in conjunction with the unframed Master
and Slave modes:
• SPI Master, Frame Master
• SPI Master, Frame Slave
• SPI Slave, Frame Master
• SPI Slave, Frame Slave
These modes determine whether or not the SPI1 module generates the serial clock and the
frame synchronization pulse.
When FRMEN (SPI1CON2<15>) = 1 and MSTEN (SPI1CON1<5>) = 1, the SCK1 pin becomes
an output and the SPI clock at SCK1 becomes a free running clock.
When FRMEN = 1 and MSTEN = 0, the SCK1 pin becomes an input. The source clock provided
to the SCK1 pin is assumed to be a free running clock.
The polarity of the clock is selected by the CKP (SPI1CON1<6>) bit. The CKE (SPI1CON1<8>)
bit is not used for the Framed SPI modes and should be programmed to ‘0’ by the user
application.
When CKP = 0, the frame synchronization pulse output and the SDO1 data output change on
the rising edge of the clock pulses at the SCK1 pin. Input data is sampled at the SDI1 input pin
on the falling edge of the serial clock.
When CKP = 1, the frame synchronization pulse output and the SDO1 data output change on
the falling edge of the clock pulses at the SCK1 pin. Input data is sampled at the SDI1 input pin
on the rising edge of the serial clock.
When SPIFSD (SPI1CON2<14>) = 0, the SPI1 module is in the Frame Master mode of
operation. In this mode, the frame sync pulse is initiated by the module when the user application
writes the transmit data to the SPI1BUF location (thus writing the SPI1TXB register with transmit
data). At the end of the frame synchronization pulse, the SPI1TXB is transferred to the SPI1SR
and data transmission or reception begins.
When SPIFSD = 1, the module is in Framed Slave mode. In this mode, the frame synchronization
pulse is generated by an external source. When the module samples the frame synchronization
pulse, it will transfer the contents of the SPI1TXB register to the SPI1SR and data transmission
or reception begins. The user application must make sure that the correct transmission data is
loaded into the SPI1BUF before the frame synchronization pulse is received.
Note:
Note:
The use of the SS1 and SCK1 pins is mandatory in all Framed SPI modes.
Receiving a frame synchronization pulse will start a transmission regardless of
whether data was written to SPI1BUF. If no write was performed, the old contents of
the SPI1TXB will be transmitted.
© 2008 Microchip Technology Inc.