PIC18LF4510-I/PT Microchip Technology, PIC18LF4510-I/PT Datasheet - Page 269
![IC MCU FLASH 16KX16 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18LF4510-I/PT
Manufacturer Part Number
PIC18LF4510-I/PT
Description
IC MCU FLASH 16KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18LF2410-ISO.pdf
(376 pages)
4.PIC18LF2410-ISO.pdf
(8 pages)
5.PIC18LF2410-ISO.pdf
(16 pages)
6.PIC18LF2410-ISO.pdf
(6 pages)
7.PIC18LF2410-ISO.pdf
(6 pages)
8.PIC18LF2410-ISO.pdf
(8 pages)
Specifications of PIC18LF4510-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Core
PIC
Processor Series
PIC18LF
Data Bus Width
8 bit
Maximum Clock Frequency
40 MHz
Data Ram Size
1.5 KB
Data Rom Size
1536 B
On-chip Adc
13 bit
Number Of Programmable I/os
36
Number Of Timers
1 x 8
Operating Supply Voltage
2 V to 5.5 V
Mounting Style
SMD/SMT
Height
1 mm
Interface Type
CCP, ECCP, EUSART, I2C, MSSP, SPI
Length
10 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF4510-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18LF2410-ISO PDF datasheet #3
- PIC18LF2410-ISO PDF datasheet #4
- PIC18LF2410-ISO PDF datasheet #5
- PIC18LF2410-ISO PDF datasheet #6
- PIC18LF2410-ISO PDF datasheet #7
- PIC18LF2410-ISO PDF datasheet #8
- Current page: 269 of 376
- Download datasheet (7Mb)
BRA
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2009 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
operation
Decode
No
PC
PC
Q1
Read literal
operation
Unconditional Branch
BRA
-1024 ≤ n ≤ 1023
(PC) + 2 + 2n → PC
None
Add the 2’s complement number ‘2n’ to
the PC. Since the PC will have incre-
mented to fetch the next instruction, the
new address will be PC + 2 + 2n. This
instruction is a two-cycle instruction.
1
2
HERE
1101
No
Q2
‘n’
=
=
n
address (HERE)
address (Jump)
0nnn
BRA
operation
Process
Data
No
Q3
Jump
nnnn
Write to PC
operation
No
Q4
nnnn
BSF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
PIC18F2X1X/4X1X
Decode
FLAG_REG
FLAG_REG
Q1
register ‘f’
Bit Set f
BSF
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
1 → f<b>
None
Bit ‘b’ in register ‘f’ is set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
BSF
Read
1000
Q2
=
=
f, b {,a}
0Ah
8Ah
FLAG_REG, 7, 1
bbba
Process
Data
Q3
DS39636D-page 271
ffff
register ‘f’
Write
Q4
ffff
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