PIC18C442-I/PT Microchip Technology, PIC18C442-I/PT Datasheet - Page 110

• Manufacturer Part Number: PIC18C442-I/PT
• Description: IC MCU OTP 8KX16 A/D 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C442-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: MSSP, SPI, I2C, PSP, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• For Use With: I3DB18C452 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18CXX2
13.1
Capture/Compare/PWM Register 1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
TABLE 13-1:
TABLE 13-2:
DS39026C-page 108
CCPx Mode CCPy Mode
Compare
Capture
Capture
PWM
PWM
PWM
CCP Mode
Compare
Capture
CCP1 Module
PWM
Compare
Compare
Compare
Capture
Capture
CCP MODE - TIMER
RESOURCE
INTERACTION OF TWO CCP MODULES
PWM
TMR1 or TMR3 time-base. Time-base can be different for each CCP.
which clears either TMR1, or TMR3, depending upon which time-base is used.
The compare(s) could be configured for the special event trigger,
which clears TMR1, or TMR3, depending upon which time-base is used.
None.
The compare could be configured for the special event trigger,
The PWMs will have the same frequency and update rate (TMR2 interrupt).
None.
Timer1 or Timer3
Timer1 or Timer3
Timer Resource
Timer2
13.2
Capture/Compare/PWM Register2 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.
Interaction
CCP2 Module
2001 Microchip Technology Inc.