PIC18LF2455-I/SO Microchip Technology, PIC18LF2455-I/SO Datasheet - Page 9
![IC PIC MCU FLASH 12KX16 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18LF2455-I/SO
Manufacturer Part Number
PIC18LF2455-I/SO
Description
IC PIC MCU FLASH 12KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XR1.pdf
(438 pages)
3.PIC18F2221-ISO.pdf
(46 pages)
4.PIC18F2455-ISO.pdf
(14 pages)
5.PIC18F2455-ISO.pdf
(8 pages)
6.PIC18F2455-ISO.pdf
(26 pages)
7.PIC18LF2455-ISO.pdf
(430 pages)
Specifications of PIC18LF2455-I/SO
Core Size
8-Bit
Program Memory Size
24KB (12K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
PIC18
No. Of I/o's
24
Eeprom Memory Size
256Byte
Ram Memory Size
2KB
Cpu Speed
48MHz
No. Of Timers
4
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
2048 B
Interface Type
SPI, I2C, EAUSART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Number Of Timers
1 x 8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Package
28SOIC W
Device Core
PIC
Family Name
PIC18
Maximum Speed
48 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF2455-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
20. Module: EUSART
21. Module: EUSART
22. Module: EUSART
© 2008 Microchip Technology Inc.
Note:
In 9-Bit Asynchronous Full-Duplex Receive mode,
the received data may be corrupted if the TX9D bit
(TXSTA<0>) is not modified immediately after the
RCIDL bit (BAUDCON<6>) is set.
Work around
Write to TX9D only when a reception is not in prog-
ress (RCIDL = 1). Since there is no interrupt asso-
ciated with RCIDL, it must be polled in software to
determine when TX9D can be updated.
Date Codes that pertain to this issue:
All engineering and production devices.
After the last received byte has been read from the
EUSART receive buffer, RCREG, the value is no
longer valid for subsequent read operations.
Work around
The RCREG register should only be read once for
each byte received. After each byte is received
from the EUSART, store the byte into a user vari-
able. To determine when a byte is available to read
from RCREG, poll the RCIDL bit (BAUDCON<6>)
for a low-to-high transition, or use the EUSART
Receive Interrupt Flag, RCIF (PIR1<5>).
Date Codes that pertain to this issue:
All engineering and production devices.
With the auto-wake-up option enabled by setting
the
(PIR1<5>) bit will become set on a high-to-low
transition on the RX pin. However, the WUE bit
may not clear within 1 T
tion on RX. While the WUE bit is set, reading the
receive buffer, RCREG, will not clear the RCIF
interrupt flag. Therefore, the first opportunity to
automatically clear RCIF by reading RCREG may
take longer than expected.
Work around
There are two workarounds available:
1. Clear the WUE bit in software, after the wake-
2. Poll the WUE bit and read RCREG after the
Date Codes that pertain to this issue:
All engineering and production devices.
up event has occurred, prior to reading the
receive buffer, RCREG.
WUE bit is automatically cleared.
WUE
RCIF can only be cleared by reading
RCREG.
bit
(BAUDCON<1>),
CY
of a low-to-high transi-
the
PIC18F2455/2550/4455/4550
RCIF
23. Module: Timer1
24. Module: Reset
25. Module: ECCP (PWM Mode)
In 16-Bit Asynchronous Counter mode (with or
without use of the Timer1 oscillator), the TMR1H
and TMR3H buffers do not update when TMRxL is
read.
This issue only affects reading the TMRxH
registers. The timers increment and set the
interrupt flags as expected. The timer registers can
also be written as expected.
Work around
1. Use 8-bit mode by clearing the RD16 bit
2. Use the internal clock synchronization option
Date Codes that pertain to this issue:
All engineering and production devices.
This version of silicon does not support the func-
tionality described in Note 1 of parameter D002 in
Section 28.1 “DC Characteristics: Supply
Voltage” of the data sheet. The RAM content may
be altered during a Reset event if the following
conditions are met.
• Device is accessing RAM.
• Asynchronous Reset (i.e., WDT, BOR or
Work around
None
Date Codes that pertain to this issue:
All engineering and production devices.
When configured for half-bridge operation with
dead band (CCPxCON<7:6> = 10), the PWM
output may be corrupted for certain values of the
PWM duty cycle. This can occur when these
additional criteria are also met:
• a non-zero dead-band delay is specified
• the duty cycle has a value of 0 through 3, or
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
MCLR) occurs when a write operation is being
executed (start of a Q4 cycle) or if a RESET
instruction is executed and immediately
followed by a RETURN instruction.
(PDC6:PDC0 > 0); and
4n + 3 (n ≥ 1).
(T1CON<7>).
by clearing the T1SYNC bit (T1CON<2>).
DS80220J-page 9