DSPIC30F2020-30I/MM Microchip Technology, DSPIC30F2020-30I/MM Datasheet - Page 31
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DSPIC30F2020-30I/MM
Manufacturer Part Number
DSPIC30F2020-30I/MM
Description
IC DSPIC MCU/DSP 12K 28QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.AC164335.pdf
(286 pages)
2.DM300023.pdf
(22 pages)
3.DM300023.pdf
(18 pages)
4.DSPIC30F2011-20ISO.pdf
(66 pages)
5.DSPIC30F2011-20IP.pdf
(26 pages)
6.DSPIC30F1010-30ISO.pdf
(26 pages)
7.DSPIC30F1010-30ISO.pdf
(50 pages)
Specifications of DSPIC30F2020-30I/MM
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
Core Frequency
15MHz
Core Supply Voltage
3.3V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
21
Flash Memory Size
12KB
Supply Voltage Range
3V To 3.6V
Package
28QFN-S EP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
30 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
21
Interface Type
I2C/SPI/UART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300023 - KIT DEMO DSPICDEM SMPS BUCKAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F2020-30I/MMB32
Manufacturer:
Microchip Technology
Quantity:
135
11.6
Instead of using a Bulk Erase operation, each region of
memory can be individually erased by row. In this case,
all of the code memory, executive memory and
Configuration registers must be erased one row at a
time. The procedure for erasing individual rows of
program memory is quite different from the procedure
for erasing the entire chip. This procedure is detailed in
TABLE 11-5:
© 2010 Microchip Technology Inc.
Step 1: Exit the Reset vector.
0000
0000
0000
Step 2: Initialize NVMADR and NVMADRU to erase code memory and initialize W7 for row address updates.
0000
0000
0000
0000
Step 3: Set NVMCON to erase 1 row of code memory.
0000
0000
Step 4: Unlock the NVMCON to erase 1 row of code memory.
0000
0000
0000
0000
Step 5: Initiate the erase cycle.
0000
0000
0000
0000
0000
—
0000
0000
0000
0000
0000
Command
(Binary)
Row Erasing Program Memory
040100
040100
000000
EB0300
883B16
883B26
200407
24071A
883B0A
200558
883B38
200AA9
883B39
A8E761
000000
000000
000000
000000
—
A9E761
000000
000000
000000
000000
SERIAL INSTRUCTION EXECUTION FOR ROW ERASING PROGRAM MEMORY
(Hex)
Data
GOTO 0x100
GOTO 0x100
NOP
CLR
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
BSET NVMCON, #WR
NOP
NOP
NOP
NOP
Externally time 'P19a' msec
Requirements”)
BCLR NVMCON, #WR
NOP
NOP
NOP
NOP
W6
W6, NVMADR
W6, NVMADRU
#0x40, W7
#0x4071, W10
W10, NVMCON
#0x55, W8
W8, NVMKEY
#0xAA, W9
W9, NVMKEY
Table
Step 3 must be modified with the appropriate NVMCON
value as per
However, since this method is more time consuming
and does not clear the code-protect bits, it is not
recommended in most cases.
Note 1: Program memory must be erased before
(see
11-5. If a Segment Erase operation is required,
Description
Section 13.0 “AC/DC Characteristics and Timing
writing any data to program memory.
Table
11-2.
DS70284C-page 31