PIC16C77-04E/P Microchip Technology, PIC16C77-04E/P Datasheet - Page 41
![IC MCU OTP 8KX14 A/D PWM 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC16C77-04E/P
Manufacturer Part Number
PIC16C77-04E/P
Description
IC MCU OTP 8KX14 A/D PWM 40DIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16C72-04SO.pdf
(289 pages)
4.PIC16C77-04P.pdf
(8 pages)
Specifications of PIC16C77-04E/P
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
14KB (8K x 14)
Program Memory Type
OTP
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16C72-04SO PDF datasheet #3
- PIC16C77-04P PDF datasheet #4
- Current page: 41 of 289
- Download datasheet (3Mb)
Example 4-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that PCLATH is saved and restored by the interrupt ser-
vice routine (if interrupts are used).
EXAMPLE 4-1:
ORG 0x500
BSF
BCF
CALL
ORG 0x900
SUB1_P1:
RETURN
FIGURE 4-18: DIRECT/INDIRECT ADDRESSING
1997 Microchip Technology Inc.
RP1:RP0
bank select
For register file map detail see Figure 4-4, and Figure 4-5.
PCLATH,3
PCLATH,4
SUB1_P1
:
:
:
:
:
location select
6
Direct Addressing
Data
Memory
CALL OF A SUBROUTINE IN
PAGE 1 FROM PAGE 0
;Select page 1 (800h-FFFh)
;Only on >4K devices
;Call subroutine in
;page 1 (800h-FFFh)
;called subroutine
;page 1 (800h-FFFh)
;return to Call subroutine
;in page 0 (000h-7FFh)
from opcode
00h
7Fh
Bank 0
00
0
80h
FFh
Bank 1
01
100h
17Fh
Bank 2
10
not used
4.5
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Reg-
ister, FSR. Reading the INDF register itself indirectly
(FSR = '0') will read 00h. Writing to the INDF register
indirectly results in a no-operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 4-18.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-2.
EXAMPLE 4-2:
NEXT
CONTINUE
180h
1FFh
Bank 3
11
Indirect Addressing, INDF and FSR
Registers
Applicable Devices
72 73 73A 74 74A 76 77
movlw
movwf
clrf
incf
btfss
goto
:
IRP
bank select
0x20
FSR
INDF
FSR,F
FSR,4
NEXT
INDIRECT ADDRESSING
7
Indirect Addressing
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
PIC16C7X
;yes continue
FSR register
DS30390E-page 41
location select
0
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