PIC18F452-E/P Microchip Technology, PIC18F452-E/P Datasheet - Page 136
![IC MCU CMOS 40MHZ 16K FLSH 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F452-E/P
Manufacturer Part Number
PIC18F452-E/P
Description
IC MCU CMOS 40MHZ 16K FLSH 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F242-ISO.pdf
(332 pages)
3.PIC18F242-ISO.pdf
(14 pages)
4.PIC18F242-ISO.pdf
(16 pages)
5.PIC18F242-ISO.pdf
(16 pages)
6.PIC18F242-ISO.pdf
(14 pages)
7.PIC18LF242-ISO.pdf
(36 pages)
8.PIC18F452-EP.pdf
(332 pages)
Specifications of PIC18F452-E/P
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
34
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
MSSP/SPI/I2C/PSP/USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
34
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
40PDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F452-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F242-ISO PDF datasheet #2
- PIC18F242-ISO PDF datasheet #3
- PIC18F242-ISO PDF datasheet #4
- PIC18F242-ISO PDF datasheet #5
- PIC18F242-ISO PDF datasheet #6
- PIC18LF242-ISO PDF datasheet #7
- PIC18F452-EP PDF datasheet #8
- Current page: 136 of 332
- Download datasheet (6Mb)
PIC18FXX2
15.4
The MSSP module in I
master and slave functions (including general call sup-
port) and provides interrupts on START and STOP bits
in hardware to determine a free bus (multi-master func-
tion). The MSSP module implements the Standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCL) - RC3/SCK/SCL
• Serial data (SDA) - RC4/SDI/SDA
The user must configure these pins as inputs or outputs
through the TRISC<4:3> bits.
FIGURE 15-7:
DS39564C-page 134
RC3/SCK/SCL
RC4/
SDI/
SDA
I
2
C Mode
Read
Shift
Clock
MSb
MSSP BLOCK DIAGRAM
(I
STOP bit Detect
2
2
Match Detect
SSPADD reg
SSPBUF reg
START and
SSPSR reg
C mode fully implements all
C MODE)
LSb
Write
(SSPSTAT reg)
Internal
Data Bus
S, P bits
Set, Reset
Addr Match
15.4.1
The MSSP module has six registers for I
These are:
• MSSP Control Register1 (SSPCON1)
• MSSP Control Register2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• MSSP Shift Register (SSPSR) - Not directly
• MSSP Address Register (SSPADD)
SSPCON, SSPCON2 and SSPSTAT are the control
and status registers in I
SSPCON and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are read
only. The upper two bits of the SSPSTAT are read/
write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
SSPADD register holds the slave device address
when the SSP is configured in I
the SSP is configured in Master mode, the lower
seven bits of SSPADD act as the baud rate generator
reload value.
In receive operations, SSPSR and SSPBUF together,
create a double buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not double buff-
ered. A write to SSPBUF will write to both SSPBUF and
SSPSR.
accessible
REGISTERS
© 2006 Microchip Technology Inc.
2
C mode operation. The
2
C Slave mode. When
2
C operation.
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