ATMEGA64L-8MQR Atmel, ATMEGA64L-8MQR Datasheet - Page 18
![MCU AVR 64KB FLASH 8MHZ 64QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA64L-8MQR
Manufacturer Part Number
ATMEGA64L-8MQR
Description
MCU AVR 64KB FLASH 8MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA64L-8MQR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Errata
ATmega64, rev. A
to C, E
18
ATmega64(L)
The revision letter in this section refers to the revision of the ATmega64 device.
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1. First Analog Comparator conversion may be delayed
2. Interrupts may be lost when writing the timer registers in the asynchronous timer
3. Stabilizing time needed when changing XDIV Register
First Analog Comparator conversion may be delayed
Interrupts may be lost when writing the timer registers in the asynchronous timer
Stabilizing time needed when changing XDIV Register
Stabilizing time needed when changing OSCCAL Register
IDCODE masks data from TDI input
Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request
If the device is powered by a slow rising V
take longer than expected on some devices.
Problem Fix/Workaround
When the device has been powered or reset, disable then enable the Analog Comparator
before the first conversion.
The interrupt will be lost if a timer register that is synchronous timer clock is written when the
asynchronous Timer/Counter register (TCNTx) is 0x00.
Problem Fix/Workaround
Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor
0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous
Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx).
After increasing the source clock frequency more than 2% with settings in the XDIV register,
the device may execute some of the subsequent instructions incorrectly.
Problem Fix / Workaround
The NOP instruction will always be executed correctly also right after a frequency change.
Thus, the next 8 instructions after the change should be NOP instructions. To ensure this,
follow this procedure:
1.Clear the I bit in the SREG Register.
2.Set the new pre-scaling factor in XDIV register.
3.Execute 8 NOP instructions
4.Set the I bit in SREG
This will ensure that all subsequent instructions will execute correctly.
Assembly Code Example:
CLI
OUT
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
SEI
XDIV, temp
; clear global interrupt enable
; set new prescale value
; no operation
; no operation
; no operation
; no operation
; no operation
; no operation
; no operation
; no operation
; clear global interrupt enable
CC
, the first Analog Comparator conversion will
2490QS–AVR–07/10