PIC16F877-04/PT Microchip Technology, PIC16F877-04/PT Datasheet - Page 80

• Manufacturer Part Number: PIC16F877-04/PT
• Description: IC MCU FLASH 8KX14 EE 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F877-04/PT

• Core Size: 8-Bit
• Program Memory Size: 14KB (8K x 14)
• Core Processor: PIC
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC16F
• No. Of I/o's: 33
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 368Byte
• Cpu Speed: 4MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F87X
9.2.5
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET, or when the MSSP module is
disabled. Control of the I
P bit is set, or the bus is idle, with both the S and P bits
clear.
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
FIGURE 9-9:
9.2.6
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET or
when the MSSP module is disabled. Control of the I
bus may be taken when bit P (SSPSTAT<4>) is set, or
the bus is idle with both the S and P bits clear. When
the bus is busy, enabling the SSP Interrupt will gener-
ate the interrupt when the STOP condition occurs.
DS30292C-page 78
SDA
SCL
MASTER MODE
MULTI-MASTER MODE
SSP BLOCK DIAGRAM (I
2
C bus may be taken when the
SDA in
SCL in
Bus Collision
Read
MSb
START bit, STOP bit,
Write Collision Detect
START bit Detect,
end of XMIT/RCV
State Counter for
Clock Arbitration
STOP bit Detect
2
Acknowledge
2
C
SSPBUF
C MASTER MODE)
Generate
SSPSR
LSb
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (an SSP interrupt will occur if
enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated START
In Multi-Master operation, the SDA line must be moni-
tored for arbitration to see if the signal level is the
expected output level. This check is performed in hard-
ware, with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A START Condition
• A Repeated START Condition
• An Acknowledge Condition
Write
Clock
Data Bus
Shift
Internal
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
2001 Microchip Technology Inc.
SSPADD<6:0>
SSPM3:SSPM0,
Baud
Rate
Generator