ATMEGA325P-20MU Atmel, ATMEGA325P-20MU Datasheet - Page 185

• Manufacturer Part Number: ATMEGA325P-20MU
• Description: IC MCU AVR 32K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA325P-20MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA325P-16MU; ATMEGA325P-16MU

8023F–AVR–07/09
• Bit 5:4 – UPMn1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPMn0 setting.
If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
Figure 18-10. UPMn Bits Settings
• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores
this setting.
Figure 18-11. USBSn Bit Settings
• Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
Figure 18-12. UCSZ Bits Settings
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOLn bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCK).
UCSZn2
UPMn1
0
0
1
1
0
0
0
0
1
1
1
1
USBSn
0
1
UCSZn1
UPMn0
0
1
0
1
0
0
1
1
0
0
1
1
Parity Mode
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
Stop Bit(s)
1-bit
2-bit
UCSZn0
ATmega325P/3250P
0
1
0
1
0
1
0
1
Character Size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
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