ATMEGA325PV-10AU Atmel, ATMEGA325PV-10AU Datasheet - Page 284

• Manufacturer Part Number: ATMEGA325PV-10AU
• Description: IC MCU AVR 32K FLASH 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA325PV-10AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, USI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 54
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 10MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA325PV-8AU; ATMEGA325PV-8AU

284
ATmega325P/3250P
Figure 25-8. Parallel Programming Timing, Loading Sequence with Timing Requirements
Note:
Figure 25-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Note:
Table 25-13. Parallel Programming Characteristics, V
Symbol
V
I
t
t
t
t
t
PP
DVXH
XLXH
XHXL
XLDX
XLWL
PP
XTAL1
PAGEL
DATA
XTAL1
DATA
BS1
XA0
XA1
BS1
XA0
XA1
OE
1. The timing requirements shown in
1. The timing requirements shown in
ing operation.
ing operation.
Parameter
Programming Enable Voltage
Programming Enable Current
Data and Control Valid before XTAL1 High
XTAL1 Low to XTAL1 High
XTAL1 Pulse Width High
Data and Control Hold after XTAL1 Low
XTAL1 Low to WR Low
Timing Requirements
ADDR0 (Low Byte)
LOAD ADDRESS
ADDR0 (Low Byte)
LOAD ADDRESS
(LOW BYTE)
(LOW BYTE)
t
XLOL
t
OLDV
(1)
(LOW BYTE)
LOAD DATA
DATA (Low Byte)
(LOW BYTE)
DATA (Low Byte)
READ DATA
Figure 25-7
Figure 25-7
t
XLXH
t
BVDV
(i.e., t
(i.e., t
(HIGH BYTE)
LOAD DATA
CC
= 5V ± 10%
DATA (High Byte)
DVXH
DVXH
(HIGH BYTE)
READ DATA
DATA (High Byte)
t
XLPH
, t
, t
LOAD DATA
XHXL
XHXL
11.5
Min
200
150
67
67
0
, and t
, and t
t
OHDZ
t
PLXH
Typ
XLDX
XLDX
LOAD ADDRESS
LOAD ADDRESS
(LOW BYTE)
(LOW BYTE)
) also apply to read-
) also apply to load-
ADDR1 (Low Byte)
ADDR1 (Low Byte)
Max
12.5
250
8023F–AVR–07/09
Units
μA
ns
ns
ns
ns
ns
V
(1)