DSPIC30F5016-20E/PT Microchip Technology, DSPIC30F5016-20E/PT Datasheet - Page 4
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DSPIC30F5016-20E/PT
Manufacturer Part Number
DSPIC30F5016-20E/PT
Description
IC DSPIC MCU/DSP 66K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F5016-30IPT.pdf
(230 pages)
4.DSPIC30F5016-30IPT.pdf
(14 pages)
5.DSPIC30F5016-30IPT.pdf
(6 pages)
6.DSPIC30F5016-30IPT.pdf
(18 pages)
Specifications of DSPIC30F5016-20E/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
66KB (22K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
For Use With
AC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F5016-20E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
dsPIC30F5015/5016
Silicon Errata Issues
1. Module: CPU
DS80452C-page 4
Note:
When a user executes a DISI #7, for example,
this will disable interrupts for 7 + 1 cycles (7 + the
DISI instruction itself). In this case, the DISI
instruction uses a counter which counts down from
7 to 0. The counter is loaded with 7 at the end of
the DISI instruction.
If the user code executes another DISI on the
instruction cycle where the DISI state machine
does not properly re-engage and continue to
disable interrupts. At this point, all interrupts are
enabled. The next time the user code executes a
DISI instruction, the feature will act normally and
block interrupts.
In summary, it is only when a DISI execution is
coincident with the current DISI count = 0, that
the issue occurs. Executing a DISI instruction
before the DISI counter reaches zero will not
produce this error. In this case, the DISI counter
is loaded with the new value, and interrupts remain
disabled until the counter becomes zero.
Work around
When executing multiple DISI instructions within
the source code, make sure that subsequent DISI
instructions have at least one instruction cycle
between the time that the DISI counter
decrements to zero and the next DISI instruction.
Alternatively, make sure that subsequent DISI
instructions are called before the DISI counter
decrements to zero.
Affected Silicon Revisions
A0
X
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A0).
2. Module: Output Compare
3. Module: Output Compare
A glitch will be produced on an output compare pin
under the following conditions:
• The user software initially drives the I/O pin
• The output compare module is configured
When these events occur, the output compare
module will drive the pin low for one instruction
cycle (T
Work around
None. However, the user may use a Timer
interrupt and write to the associated PORT register
to control the pin manually.
Affected Silicon Revisions
If the desired duty cycle is ‘0’ (OCxRS = 0), the
module will generate a high level glitch of 1 T
The second problem is that on the next cycle after
the glitch, the OC pin does not go high, or in other
words, it misses the next compare for any value
written on OCxRS.
Work around
There are two possible solutions to this problem:
1. Load a value greater than ‘0’ to the OCxRS
2. If the application requires 0% duty cycles, the
Affected Silicon Revisions
A0
A0
high using the output compare module or a
write to the associated PORT register.
and enabled to drive the pin low at some
point in later time (OCxCON = 0x0002 or
OCxCON = 0x0003).
X
X
register when operating in PWM mode. In this
case, no 0% duty cycle is achievable.
output compare module can be disabled for
0% duty cycles, and re-enabled for non-zero
percent duty cycles.
CY
) after the module is enabled.
© 2010 Microchip Technology Inc.
CY
.