PIC16F877T-20/PQ Microchip Technology, PIC16F877T-20/PQ Datasheet - Page 86
![IC MCU FLASH 8KX14 EE 44-MQFP](/photos/6/59/65984/150-44-pqfp_sml.jpg)
PIC16F877T-20/PQ
Manufacturer Part Number
PIC16F877T-20/PQ
Description
IC MCU FLASH 8KX14 EE 44-MQFP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16C770-ISO.pdf
(8 pages)
4.PIC16F873-04SO.pdf
(218 pages)
5.PIC16F873-04SO.pdf
(5 pages)
6.PIC16F873-04SO.pdf
(5 pages)
Specifications of PIC16F877T-20/PQ
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
44-MQFP, 44-PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F877T-20/PQ
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16C770-ISO PDF datasheet #3
- PIC16F873-04SO PDF datasheet #4
- PIC16F873-04SO PDF datasheet #5
- PIC16F873-04SO PDF datasheet #6
- Current page: 86 of 218
- Download datasheet (4Mb)
PIC16F87X
9.2.12
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPCON2<3>).
The baud rate generator begins counting, and on each
rollover, the state of the SCL pin changes (high to low/
low to high), and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag is set,
the SSPIF is set, and the baud rate generator is sus-
pended from counting, holding SCL low. The SSP is
now in IDLE state, awaiting the next command. When
the buffer is read by the CPU, the BF flag is automati-
cally cleared. The user can then send an Acknowledge
bit at the end of reception, by setting the Acknowledge
Sequence Enable bit, ACKEN (SSPCON2<4>).
DS30292C-page 84
Note:
The SSP module must be in an IDLE state
before the RCEN bit is set, or the RCEN bit
will be disregarded.
I
2
C MASTER MODE RECEPTION
9.2.12.1
In receive operation, BF is set when an address or data
byte is loaded into SSPBUF from SSPSR. It is cleared
when SSPBUF is read.
9.2.12.2
In receive operation, SSPOV is set when 8 bits are
received into the SSPSR, and the BF flag is already set
from a previous reception.
9.2.12.3
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), then WCOL is set and the contents of the buffer
are unchanged (the write doesn’t occur).
BF Status Flag
SSPOV Status Flag
WCOL Status Flag
2001 Microchip Technology Inc.
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