DSPIC33FJ64MC710A-E/PF Microchip Technology, DSPIC33FJ64MC710A-E/PF Datasheet - Page 33
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DSPIC33FJ64MC710A-E/PF
Manufacturer Part Number
DSPIC33FJ64MC710A-E/PF
Description
IC DSPIC MCU/DSP 64K 100-TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet
1.DSPIC33FJ64MC506A-IPT.pdf
(352 pages)
Specifications of DSPIC33FJ64MC710A-E/PF
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
100-TQFP, 100-VQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
85
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
85
Data Ram Size
16 KB
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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3.6.1
The 17-bit x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the
multiplier input value. The output of the 17-bit x 17-bit
multiplier/scaler
sign-extended to 40 bits. Integer data is inherently rep-
resented as a signed two’s complement value, where
the MSb is defined as a sign bit. Generally speaking,
the range of an N-bit two’s complement integer is -2
to 2
-32768 (0x8000) to 32767 (0x7FFF) including 0. For a
32-bit integer, the data range is -2,147,483,648
(0x8000 0000) to 2,147,483,647 (0x7FFF FFFF).
When the multiplier is configured for fractional multipli-
cation, the data is represented as a two’s complement
fraction, where the MSb is defined as a sign bit and the
radix point is implied to lie just after the sign bit (QX
format). The range of an N-bit two’s complement
fraction with this implied radix point is -1.0 to (1 – 2
For a 16-bit fraction, the Q15 data range is -1.0
(0x8000) to 0.999969482 (0x7FFF) including 0 and has
a precision of 3.01518 x 10
16 x 16 multiply operation generates a 1.31 product
which has a precision of 4.65661 x 10
The same multiplier is used to support the MCU
multiply instructions which include integer 16-bit
signed, unsigned and mixed sign multiplies.
The MUL instruction may be directed to use byte or
word-sized operands. Byte operands will direct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
3.6.2
The data accumulator consists of a 40-bit adder/
subtracter with automatic sign extension logic. It can
select one of two accumulators (A or B) as its
pre-accumulation source and post-accumulation desti-
nation. For the ADD and LAC instructions, the data to be
accumulated or loaded can be optionally scaled via the
barrel shifter prior to accumulation.
2009 Microchip Technology Inc.
N-1
– 1. For a 16-bit integer, the data range is
MULTIPLIER
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
is
a
dsPIC33FJXXXMCX06A/X08A/X10A
33-bit
-5
. In Fractional mode, the
value
-10
.
which
1-N
Preliminary
N-1
is
).
3.6.2.1
The adder/subtracter is a 40-bit adder with an optional
zero input into one side, and either true, or complement
data into the other input. In the case of addition, the
Carry/Borrow input is active-high and the other input is
true data (not complemented); whereas in the case of
subtraction, the Carry/Borrow input is active-low and
the other input is complemented. The adder/subtracter
generates Overflow Status bits, SA/SB and OA/OB,
which are latched and reflected in the STATUS register:
• Overflow from bit 39: this is a catastrophic
• Overflow into guard bits 32 through 39: this is a
The adder has an additional saturation block which
controls accumulator data saturation, if selected. It
uses the result of the adder, the Overflow Status bits
described above and the SAT<A:B> (CORCON<7:6>)
and ACCSAT (CORCON<4>) mode control bits to
determine when and to what value to saturate.
Six STATUS register bits have been provided to
support saturation and overflow; they are:
1.
2.
3.
4.
5.
6.
The OA and OB bits are modified each time data passes
through the adder/subtracter. When set, they indicate
that the most recent operation has overflowed into the
accumulator guard bits (bits 32 through 39). The OA and
OB bits can also optionally generate an arithmetic
warning trap when they and the corresponding Overflow
Trap Flag Enable bits (OVATE, OVBTE) in the INTCON1
register (refer to Section 7.0 “Interrupt Controller”)
are set. This allows the user to take immediate action, for
example, to correct system gain.
overflow in which the sign of the accumulator is
destroyed.
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
OA:
AccA overflowed into guard bits
OB:
AccB overflowed into guard bits
SA:
AccA saturated (bit 31 overflow and saturation)
or
AccA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
SB:
AccB saturated (bit 31 overflow and saturation)
or
AccB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
OAB:
Logical OR of OA and OB
SAB:
Logical OR of SA and SB
Adder/Subtracter, Overflow and
Saturation
DS70594B-page 33
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