DSPIC30F2023-30I/ML Microchip Technology, DSPIC30F2023-30I/ML Datasheet - Page 4

• Manufacturer Part Number: DSPIC30F2023-30I/ML
• Description: IC DSPIC MCU/DSP 12K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2023-30I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Core Frequency: 30MHz
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 35
• Flash Memory Size: 12KB
• Supply Voltage Range: 3V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Package: 44QFN EP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 35
• Interface Type: I2C/SPI/UART
• On-chip Adc: 12-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC30F1010/202X
TABLE 2:
DS80445D-page 4
Note 1:
RB7 Pin and All
CPU – DAW.b
EXTREF Pin
Sleep Mode
Comparator
Multiplexed
Operations
MCLR Pin
Instruction
Functions
Module
Analog
ADC
PSV
I
I
I
I
I
I
I
2
2
2
2
2
2
2
C
C
C
C
C
C
C
Only those issues indicated in the last column apply to the current silicon revision.
SILICON ISSUE SUMMARY (CONTINUED)
in Sleep Mode
1-bit and 8-bit
Consumption
Bus Collision
Current-Limit
Slave Mode
PWM Fault/
ACK/NACK
Addressing
Addressing
Addressing
BOR Event
Instruction
Operation
and ADC
Feature
Triggers
Current
DAW.b
Status
—
—
—
—
Number
Item
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.
The I2CxTRN register can be written to even if a write
collision is detected.
The ACKSTAT bit does not reflect the status of a
transmission received from an I
The D_A Status bit in the I2CxSTAT register is not set
on a write to the I2CxTRN register by an I
device.
The BCL bit in I2CSTAT can be cleared only with 16-bit
operation, and can be corrupted with 1-bit or 8-bit
operations on I2CSTAT.
When the I
ing using the same address bits (A10 and A9) as other
I
expected.
The 10-bit slave does not set the RBF flag or load the
I2CxRCV register on an address match if the Least
Significant bits (LSbs) of the address are the same as
the 7-bit reserved addresses.
If the I
address of 0x102, the I2CxRCV register content for the
lower address byte is 0x01, rather than 0x02.
When the dsPIC
enabled, the MCLR pin does not operate correctly
when a brown-out condition occurs.
An address error trap occurs, in certain addressing
modes, when accessing the first four bytes of any PSV
page.
Execution of the Sleep instruction (PWRSAV #0) may
cause incorrect program operation after the device
wakes up from Sleep. The current consumption during
Sleep may also increase beyond the specifications
listed in the device data sheet.
The RB7 pin does not work. This pertains to all
multiplexed functions on RB7, as well.
The Decimal Adjust instruction, DAW.b, may
improperly clear the Carry bit, C (SR<0>).
The EXTREF pin is susceptible to voltage spikes below
V
The Analog Comparator may falsely switch state if an
ADC conversion is triggered that coincides with two
PWM edges in Independent Time Base mode.
If the ADC module is in an enabled state when the
device enters Sleep Mode, the power-down current
(I
specifications.
2
SS
PD
C devices, the A10 and A9 bits may not work as
.
) of the device may exceed the device data sheet
2
C module is configured for 10-bit slave with an
2
C module is configured for 10-bit address-
®
DSC is operated with the PLL
Issue Summary
2
C slave device.
2
© 2010 Microchip Technology Inc.
C slave
A1
Revisions
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Affected
A2
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)
A3
X
X
X
X
X
X
X
X
X
X
X
X