PIC16LF874A-I/L Microchip Technology, PIC16LF874A-I/L Datasheet - Page 194

• Manufacturer Part Number: PIC16LF874A-I/L
• Description: IC MCU FLASH 4KX14 EE A/D 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF874A-I/L

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Controller Family/series: PIC16LF
• No. Of I/o's: 33
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 192Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC16LF874A-I/LR; PIC16LF874A-I/LR; PIC16LF874AI/L

PIC16F87XA
TABLE 17-11: I
DS39582B-page 192
100
101
102
103
90
91
106
107
92
109
110
Note 1:
Param
No.
2:
T
T
T
T
T
T
T
T
T
T
T
C
SU
SU
SU
AA
R
HIGH
LOW
F
HD
HD
BUF
B
Sym
:
:
:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A fast mode (400 kHz) I
that, T
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line, T
before the SCL line is released.
:
:
STA
DAT
STO
STA
DAT
SU
2
:
Clock High Time
Clock Low Time
SDA and SCL Rise
Time
SDA and SCL Fall
Time
Start Condition Setup
Time
Start Condition Hold
Time
Data Input Hold Time
Data Input Setup Time 100 kHz mode
Stop Condition Setup
Time
Output Valid from
Clock
Bus Free Time
Bus Capacitive Loading
DAT
C BUS DATA REQUIREMENTS
250 ns, must then be met. This will automatically be the case if the device does not stretch the LOW
R MAX
Characteristic
. + T
2
C bus device can be used in a standard mode (100 kHz) I
SU
:
DAT
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
= 1000 + 250 = 1250 ns (according to the standard mode I
20 + 0.1 C
20 + 0.1 C
0.5 T
0.5 T
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
CY
CY
B
B
1000
3500
Max
300
300
300
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s
s
2
C bus system, but the requirement
 2003 Microchip Technology Inc.
Cb is specified to be from 10 to
400 pF
C
400 pF
Only relevant for Repeated Start
condition
After this period, the first clock
pulse is generated
(Note 2)
(Note 1)
Time the bus must be free before
a new transmission can start
B
is specified to be from 10 to
2
C bus specification),
Conditions