ATMEGA1281-16AUR Atmel, ATMEGA1281-16AUR Datasheet - Page 246
![MCU AVR 128K FLASH 16MHZ 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA1281-16AUR
Manufacturer Part Number
ATMEGA1281-16AUR
Description
MCU AVR 128K FLASH 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA1281-16AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATAVRDB101 - MODULE DISPLAY LCD/RGB BACKLIGHTATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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23.5
2549M–AVR–09/10
Overview of the TWI Module
Figure 23-8. Arbitration Between Two Masters
Note that arbitration is not allowed between:
•
•
•
It is the user software’s responsibility to ensure that these illegal arbitration conditions never
occur. This implies that in multi-master systems, all data transfers must use the same composi-
tion of SLA+R/W and data packets. In other words: All transmissions must contain the same
number of data packets, otherwise the result of the arbitration is undefined.
The TWI module is comprised of several submodules, as shown in
registers drawn in a thick line are accessible through the AVR data bus.
A REPEATED START condition and a data bit.
A STOP condition and a data bit.
A REPEATED START and a STOP condition.
Synchronized
SCL Line
SDA from
SDA from
Master A
Master B
SDA Line
START
ATmega640/1280/1281/2560/2561
Arbitration, SDA
Master A Loses
Figure 23-9 on page
A
SDA
247. All
246
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