PIC18LF2580-I/SO Microchip Technology, PIC18LF2580-I/SO Datasheet - Page 219
![IC PIC MCU FLASH 16KX16 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18LF2580-I/SO
Manufacturer Part Number
PIC18LF2580-I/SO
Description
IC PIC MCU FLASH 16KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F4480-IPT.pdf
(490 pages)
3.PIC18LF2480-ISP.pdf
(14 pages)
4.PIC18F2580-ESO.pdf
(483 pages)
Specifications of PIC18LF2580-I/SO
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
SPI/I2C/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163011, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC18F2221-ISO PDF datasheet
- PIC18F4480-IPT PDF datasheet #2
- PIC18LF2480-ISP PDF datasheet #3
- PIC18F2580-ESO PDF datasheet #4
- Current page: 219 of 490
- Download datasheet (9Mb)
18.4.8
To initiate a Start condition, the user sets the Start
Condition Enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, the Baud Rate Gener-
ator is reloaded with the contents of SSPADD<6:0>
and starts its count. If SCL and SDA are both sampled
high when the Baud Rate Generator times out (T
the SDA pin is driven low. The action of the SDA being
driven low while SCL is high is the Start condition and
causes the S bit (SSPSTAT<3>) to be set. Following
this, the Baud Rate Generator is reloaded with the
contents of SSPADD<6:0> and resumes its count.
When the Baud Rate Generator times out (T
SEN bit (SSPCON2<0>) will be automatically cleared
by hardware, the Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
FIGURE 18-19:
© 2009 Microchip Technology Inc.
I
CONDITION TIMING
2
C MASTER MODE START
Write to SEN bit occurs here
FIRST START BIT TIMING
SDA
SCL
PIC18F2480/2580/4480/4580
BRG
SDA = 1,
SCL = 1
T
BRG
), the
BRG
),
Set S bit (SSPSTAT<3>)
T
S
BRG
At completion of Start bit,
hardware clears SEN bit
18.4.8.1
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
and sets SSPIF bit
Note:
Note:
T
Write to SSPBUF occurs here
BRG
1st bit
If, at the beginning of the Start condition,
the SDA and SCL pins are already sam-
pled low, or if during the Start condition,
the SCL line is sampled low before the
SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag,
BCLIF, is set, the Start condition is aborted
and the I
state.
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
WCOL Status Flag
T
BRG
2
C module is reset into its Idle
2nd bit
DS39637D-page 219
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