PIC18LF2580-I/ML Microchip Technology, PIC18LF2580-I/ML Datasheet - Page 2

• Manufacturer Part Number: PIC18LF2580-I/ML
• Description: IC PIC MCU FLASH 16KX16 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2580-I/ML

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 1536Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163011, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2480/2580/4480/4580
TABLE 2:
DS80496C-page 2
MSSP
BOR
ECCP
EUSART
Timer1/3
Interrupts
ECAN™
Technology
ECAN
Technology
ECAN
Technology
ECAN
Technology
ECAN
Technology
10-Bit ADC E
MSSP
Note 1:
Module
Only those issues indicated in the last column apply to the current silicon revision.
Trip Level
Special Event
Trigger
Transmission
16-Bit Mode
Two-Cycle
Instruction
Transmit
Buffer ID
Error
Interruption
Flag
Configuration
Mode
TXBnSIDH
Register
Listen Only
Mode
SPI
I
2
IL
C™
SILICON ISSUE SUMMARY
and E
Feature
DL
Number
Item
10.
12.
13.
11.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Slave reception receives incorrect data if not
read at the correct time.
The Special Event Trigger Reset does not occur
on the next rollover of the prescaler counter.
Nine-bit timing can be corrupted if the TX9D bit
is not written immediately after TXIF is set.
The TMR1H/TMR3H Buffer registers may
lengthen the duration of the period between the
increments of the timer.
If an interrupt occurs during a two-cycle
instruction modifying the STATUS, BSR or
WREG register, the previous value is saved to
the Fast Return register.
The first five bits of a transmitted identifier may
not match the transmit buffer ID.
The error interrupt flag may not be able to be
cleared in software if the TXERRCNT or
RXERRCNT counters exceed 127.
After an error on the bus, the module is unable
to switch directly from Listen Only mode to
Configuration mode.
May become corrupted.
IRXIF, RXB0IF and RXFUL flags are
consistently set after 129 or more consistent
error frames.
E
specifications at codes, 511 and 512.
SDO output may change after inactive lock
edge of Bit 0.
Trip levels are off at high frequencies.
IL
and E
DL
may exceed data sheet
Issue Summary
 2010 Microchip Technology Inc.
A1
Affected Revisions
X
X
X
X
X
X
X
X
X
X
X
X
B0
X
X
B2
(1)
X