DSPIC33FJ128MC710-E/PF Microchip Technology, DSPIC33FJ128MC710-E/PF Datasheet - Page 16
![IC DSPIC MCU/DSP 128K 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
DSPIC33FJ128MC710-E/PF
Manufacturer Part Number
DSPIC33FJ128MC710-E/PF
Description
IC DSPIC MCU/DSP 128K 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12GP201-ISO.pdf
(90 pages)
2.DSPIC33FJ64MC506-IPT.pdf
(340 pages)
3.DSPIC33FJ64MC506-IPT.pdf
(30 pages)
Specifications of DSPIC33FJ128MC710-E/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
100-TQFP, 100-VQFP
For Use With
MA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164323 - MODULE SKT FOR 100TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
33. Module: DMA
34. Module: DMA
DS80447D-page 16
When a DMA channel is enabled in Single-Shot
mode while the device is in Idle mode, and the
corresponding peripheral is active and configured
to operate during Idle mode, the DMA channel
may not become disabled immediately upon
transferring the required amount of data.
As a result, the number of bytes or words of data
transferred may exceed the DMA transfer count
specified in the DMAxCNT register.
For example, if DMA transfers are active for both
SPI byte transmissions and receptions, and only
the receive DMA channel interrupt is enabled for
waking up the device from Idle mode, an extra byte
will be transmitted by the time the device wakes up
from Idle mode.
Work around
None.
Affected Silicon Revisions
A DMA error trap may not be generated when the
device is in Doze mode.
Work around
None.
Affected Silicon Revisions
A2
A2
X
X
A3
A3
X
X
A4
A4
X
X
35. Module: Output Compare
36. Module: UART
37. Module: UART
When the output compare module is operated in
the Dual Compare Match mode, a timer compare
match with the value in the OCxR register sets the
OCx output, producing a rising edge on the OCx
pin. Then, when a timer compare match with the
value in the OCxRS register occurs, the OCx
output is reset, producing a falling edge on the
OCx pin.
The above statement applies to all conditions
except when the difference between OCxR and
OCxRS is 1. In this case, the output compare
module may miss the Reset compare event, and
cause the OCx pin to remain continuously high.
This condition will remain until the difference
between values in the OCxR and OCxRS registers
is made greater than 1.
Work around
Ensure in software that the difference between
values in OCxR and OCxRS registers is
maintained greater than 1.
Affected Silicon Revisions
When the UART is in 4x mode (BRGH = 1) and
using two Stop bits (STSEL = 1), it may sample the
first Stop bit instead of the second one.
This issue does not affect the other UART
configurations.
Work around
Use the 16x baud rate option (BRGH = 0) and
adjust the baud rate accordingly.
Affected Silicon Revisions
When an auto-baud is detected, the receive
interrupt may occur twice. The first interrupt occurs
at the beginning of the Start bit and the second
occurs after reception of the Sync field character.
Work around
If an extra interrupt is detected, ignore the
additional interrupt.
Affected Silicon Revisions
A2
A2
A2
X
X
X
A3
A3
A3
X
X
X
A4
A4
A4
X
X
X
© 2010 Microchip Technology Inc.