PIC18LF6527-I/PT Microchip Technology, PIC18LF6527-I/PT Datasheet - Page 286
![IC PIC MCU FLASH 24KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18LF6527-I/PT
Manufacturer Part Number
PIC18LF6527-I/PT
Description
IC PIC MCU FLASH 24KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.DV164136.pdf
(446 pages)
3.PIC18F6527-IPT.pdf
(10 pages)
Specifications of PIC18LF6527-I/PT
Core Size
8-Bit
Program Memory Size
48KB (24K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
54
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3936 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
No. Of I/o's
54
Eeprom Memory Size
1024Byte
Ram Memory Size
3.84375KB
Cpu Speed
40MHz
No. Of Timers
5
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
54
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Package
64TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF6527-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18LF6527-I/PT
Manufacturer:
MIC
Quantity:
20 000
- Current page: 286 of 446
- Download datasheet (7Mb)
PIC18F8722 FAMILY
FIGURE 22-3:
22.6
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that occurred. The CMIF
bit (PIR2<6>) is the Comparator Interrupt Flag. The
CMIF bit must be reset by clearing it. Since it is also
possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
Both the CMIE bit (PIE2<6>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit (INTCON<7>) must also be set. If
any of these bits are clear, the interrupt is not enabled,
though the CMIF bit will still be set if an interrupt
condition occurs.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit, CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit, CMIF, to be cleared.
DS39646C-page 284
Note:
Port pins
Any read or write of CMCON will end the
mismatch condition.
Clear flag bit, CMIF.
Comparator Interrupts
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR2
register) interrupt flag may not get set.
Read CMCON
COMPARATOR OUTPUT BLOCK DIAGRAM
CxINV
Reset
22.7
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional if enabled. This interrupt will
wake-up the device from Sleep mode, when enabled.
Each operational comparator will consume additional
current, as shown in the comparator specifications. To
minimize power consumption while in Sleep mode, turn
off the comparators (CM<2:0> = 111) before entering
Sleep. If the device wakes up from Sleep, the contents
of the CMCON register are not affected.
22.8
A device Reset forces the CMCON register to its Reset
state, causing the comparator modules to be turned off
(CM<2:0> = 111). However, the input pins (RF3
through RF6) are configured as analog inputs by
default on device Reset. The I/O configuration for these
pins is also determined by the setting of the
PCFG<3:0> bits (ADCON1<3:0>). Therefore, device
current is minimized when analog inputs are present at
Reset time.
D
D
EN
EN
CL
Q
Q
Comparator Operation
During Sleep
Effects of a Reset
Comparator
© 2008 Microchip Technology Inc.
Other
From
CxOUT
Bus
Data
Set
CMIF
bit
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