ATMEGA645V-8MU Atmel, ATMEGA645V-8MU Datasheet - Page 165
![IC AVR MCU FLASH 64K 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA645V-8MU
Manufacturer Part Number
ATMEGA645V-8MU
Description
IC AVR MCU FLASH 64K 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA325-16MU.pdf
(362 pages)
Specifications of ATMEGA645V-8MU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SPI, UART, USI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
54
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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19.6
19.6.1
2570M–AVR–04/11
Data Transmission – The USART Transmitter
Sending Frames with 5 to 8 Data Bit
More advanced initialization routines can be made that include frame format as parameters, dis-
able interrupts and so on. However, many applications use a fixed setting of the baud and
control registers, and for these types of applications the initialization code can be placed directly
in the main routine, or be combined with initialization code for other I/O modules.
The USART Transmitter is enabled by setting the Transmit Enable (TXENn) bit in the UCSRnB
Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overrid-
den by the USART and given the function as the Transmitter’s serial output. The baud rate,
mode of operation and frame format must be set up once before doing any transmissions. If syn-
chronous operation is used, the clock on the XCK pin will be overridden and used as
transmission clock.
A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The
CPU can load the transmit buffer by writing to the UDRn I/O location. The buffered data in the
transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new
frame. The Shift Register is loaded with new data if it is in idle state (no ongoing transmission) or
immediately after the last stop bit of the previous frame is transmitted. When the Shift Register is
loaded with new data, it will transfer one complete frame at the rate given by the Baud Register,
U2Xn bit or by XCK depending on mode of operation.
The following code examples show a simple USART transmit function based on polling of the
Data Register Empty (UDREn) Flag. When using frames with less than eight bits, the most sig-
nificant bits written to the UDRn are ignored. The USART has to be initialized before the function
can be used. For the assembly code, the data to be sent is assumed to be stored in Register
R16.
Note:
Assembly Code Example
C Code Example
USART_Transmit:
void USART_Transmit( unsigned char data )
{
}
; Wait for empty transmit buffer
sbis UCSR0A,UDRE0
rjmp USART_Transmit
; Put data (r16) into buffer, sends the data
out
ret
/* Wait for empty transmit buffer */
while ( !( UCSR0A & (1<<UDRE0)) )
/* Put data into buffer, sends the data */
UDR0 = data;
1. See
UDR0,r16
;
“About Code Examples” on page
(1)
(1)
ATmega325/3250/645/6450
9.
165
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