DSPIC30F6014A-20E/PT Microchip Technology, DSPIC30F6014A-20E/PT Datasheet - Page 7

• Manufacturer Part Number: DSPIC30F6014A-20E/PT
• Description: IC DSPIC MCU/DSP 144K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6014A-20E/PT

• Program Memory Type: FLASH
• Program Memory Size: 144KB (48K x 24)
• Package / Case: 80-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 68
• Data Ram Size: 8 KB
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 80TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300024 - KIT DEMO DSPICDEM 1.1XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPDM300004-2 - BOARD DEMO DSPICDEM.NET 2DM300004-1 - BOARD DEMO DSPICDEM.NET 1AC30F007 - MODULE SKT FOR DSPIC30F 80TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register 35-3:
© 2008 Microchip Technology Inc.
Upper Byte:
bit 15
bit 15
bit 14
bit 13
bit 12-2
bit 1
bit 0
FRMEN
R/W-0
FRMEN: Framed SPI1 Support bit
1 = Framed SPI1 support is enabled (SS1 pin is used as frame sync pulse input/output)
0 = Framed SPI1 support is disabled
SPIFSD: Frame Sync Pulse Direction Control bit
1 = Frame sync pulse input (slave)
0 = Frame sync pulse output (master)
FRMPOL: Frame Sync Pulse Polarity bit
1 = Frame sync pulse is active-high
0 = Frame sync pulse is active-low
Unimplemented: Read as ‘0’
FRMDLY: Frame Sync Pulse Edge Select bit
1 = Frame sync pulse coincides with first bit clock
0 = Frame sync pulse precedes first bit clock
Unimplemented: This bit must not be set to ‘1’ by the user application
Legend:
R = Readable bit
-n = Value at POR
SPIFSD
R/W-0
SPI1CON2: SPI1 Control Register 2
Lower Byte:
bit 7
Section 35. Serial Peripheral Interface (SPI) (Part II)
U-0
—
FRMPOL
R/W-0
U-0
—
W = Writable bit
‘1’ = Bit is set
U-0
—
U-0
—
U-0
—
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
x = Bit is unknown
bit 8
FRMDLY
R/W-0
DS70272B-page 35-7
U-0
—
bit 0
35