DSPIC33FJ256GP710A-I/PT Microchip Technology, DSPIC33FJ256GP710A-I/PT Datasheet - Page 297

• Manufacturer Part Number: DSPIC33FJ256GP710A-I/PT
• Description: IC MCU 16BIT 256KB FLASH 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ256GP710A-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 30K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 3.3V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 85
• Flash Memory Size: 256KB
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: No
• Package: 100TQFP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 85
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 64-chx10-bit|64-chx12-bit
• Number Of Timers: 9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FIGURE 25-18:
TABLE 25-35: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS
 2009 Microchip Technology Inc.
AC CHARACTERISTICS
CS60
CS61
CS62
CS65
CS66
CS70
CS71
CS72
CS75
CS76
CS77
CS78
CS80
Note 1:
Param
SDIx
(CSDI)
SDOx
(CSDO)
SYNC
(COFS)
BIT_CLK
(CSCK)
No.
2:
3:
T
T
T
T
T
T
T
T
T
T
T
T
T
Symbol
SACL
SYNCLO
SYNCHI
SYNC
OVDACL
These parameters are characterized but not tested in manufacturing.
These values assume BIT_CLK frequency is 12.288 MHz.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
CS80
BCLKL
BCLKH
BCLK
HACL
RACL
FACL
RACL
FACL
LSb
CS61
BIT_CLK Low Time
BIT_CLK High Time
BIT_CLK Period
Input Setup Time to
Falling Edge of BIT_CLK
Input Hold Time from
Falling Edge of BIT_CLK
SYNC Data Output Low Time
SYNC Data Output High Time
SYNC Data Output Period
Rise Time, SYNC, SDATA_OUT
Fall Time, SYNC, SDATA_OUT
Rise Time, SYNC, SDATA_OUT
Fall Time, SYNC, SDATA_OUT
Output Valid Delay from Rising
Edge of BIT_CLK
DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS
CS65 CS66
MSb In
dsPIC33FJXXXGPX06A/X08A/X10A
Characteristic
CS60
MSb
(1,2)
CS71
CS62
CS72
Preliminary
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature
Min
36
36
—
—
—
—
—
—
—
—
—
—
—
CS76
Typ
40.7
40.7
81.4
19.5
20.8
1.3
10
10
—
—
—
—
—
(3)
Max
45
45
10
10
30
15
—
—
—
—
25
25
30
CS76
CS21
-40°C  T
-40°C  T
CS75
Units
s
s
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS20
Bit clock is input
Note 1
Note 1
Note 1
C
C
C
C
A
A
LOAD
LOAD
LOAD
LOAD
CS70
 +85°C
 +125°C for Extended
Conditions
= 50 pF, V
= 50 pF, V
= 50 pF, V
= 50 pF, V
DS70593B-page 297
—
—
—
—
—
CS75
DD
DD
DD
DD
LSb
= 5V
= 5V
= 3V
= 3V