PIC32MX575F512H-80I/PT Microchip Technology, PIC32MX575F512H-80I/PT Datasheet - Page 9

• Manufacturer Part Number: PIC32MX575F512H-80I/PT
• Description: IC MCU 32BIT 512KB FLASH 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX575F512H-80I/PT

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: CAN, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC32
• No. Of I/o's: 53
• Ram Memory Size: 64KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Digital Ic Case Style: TQFP
• Embedded Interface Type: CAN, I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

31. Module: UART
32. Module: JTAG
33. Module: UART
© 2010 Microchip Technology Inc.
In IrDA mode with baud clock output enabled, the
UART TX data is corrupted when the BRG value is
greater than 0x200.
Work around
Use the Peripheral Bus (PB) divisor to lower the
PB frequency such that the required UART BRG
value is less than 0x201.
Affected Silicon Revisions
On 64-pin devices an external pull-up resistor is
required on the TMS pin for proper JTAG.
Work around
Connect a 100k-200k pull-up to the TMS pin.
Affected Silicon Revisions
The TRMT bit is asserted during the STOP bit
generation, not after the STOP bit has been sent.
Work around
If firmware needs to be aware when the transmis-
sion is complete, firmware should add a half bit
time delay after the TRMT bit is asserted.
Affected Silicon Revisions
A0
A0
A0
X
X
X
PIC32MX575/675/695/775/795
34. Module: UART
35. Module: ADC
36. Module: JTAG
The OERR bit does not get cleared on a module
Reset. If the OERR bit is set and the module is dis-
abled, the OERR bit retains its status even after
the UART module is reinitialized.
Work around
The user software must check this bit in the UART
module initialization routine and clear it if it is set.
Affected Silicon Revisions
When the ADC module is configured to start con-
version on an external interrupt (SSRC<2:0> =
001), the start of conversion always occurs on a
rising edge detected at the INT0 pin, even when
the INT0 pin has been configured to generate an
interrupt on a falling edge (INT0EP = 0).
Work around
Generate ADC conversion triggers on the rising
edge of the INT0 signal.
Alternatively, use external circuitry to invert the sig-
nal appearing at the INT0 pin, so that a falling edge
of the input signal is detected as a rising edge by
the INT0 pin.
Affected Silicon Revisions
Pin 100 on 100-pin packages and pin A1 on
121-pin packages do not respond to boundary
scan commands.
Work around
None.
Affected Silicon Revisions
A0
A0
A0
X
X
X
DS80480E-page 9