PIC18LF4585-I/PT Microchip Technology, PIC18LF4585-I/PT Datasheet - Page 9
![IC MCU FLASH 24KX16 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18LF4585-I/PT
Manufacturer Part Number
PIC18LF4585-I/PT
Description
IC MCU FLASH 24KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F4585-IPT.pdf
(482 pages)
4.PIC18F4585-IPT.pdf
(14 pages)
5.PIC18F4585-IPT.pdf
(8 pages)
6.PIC18F4585-IPT.pdf
(12 pages)
7.PIC18F4585-IPT.pdf
(4 pages)
Specifications of PIC18LF4585-I/PT
Core Size
8-Bit
Program Memory Size
48KB (24K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
1KB
Ram Memory Size
3.25KB
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF4585-I/PT
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
PIC18LF4585-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
29. Module: Reset
30. Module: ECAN™ Technology
EXAMPLE 6:
© 2007 Microchip Technology Inc.
If (RXBnOVFL == 1)
This version of silicon does not support the func-
tionality described in Note 1 of parameter D002 in
Section 27.1
Voltage” of the Device Data Sheet. The RAM
content may be altered during a Reset event if the
following conditions are met.
• Device is accessing RAM.
• Asynchronous Reset (i.e., WDT, BOR or MCLR
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
Under specific conditions, the first five bits of a
transmitted identifier may not match the value in
the Transmit Buffer ID register, TXBnSIDH. The
following conditions must exist for the corruption to
occur:
1. A transmit message must be pending.
2. The ECAN module must detect a Start-Of-
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
occurs when a write operation is being
executed (start of a Q4 cycle).
Frame (SOF) in the third bit of interframe
space.
{
}
Temp_RXREG = RXBx; // Read receive buffer
If (MyFlag)
{
}
If (TXREQ == 1)// Is a transmission pending?
{
}
TXREQ = 1;
MyFlag = 0;
“DC
TXREQ = 0; // Clear transmit request
If (TXABT == 1)// Store transmission aborted status value
MyFlag = 1;
Characteristics:
// Has an overflow occurred?
// Was previous transmission aborted?
// Set transmit request
// Reset stored transmission aborted status
PIC18F2585/2680/4585/4680
Supply
31. Module: ECAN™ Technology
32. Module: ECAN™ Technology
Following an error on the bus, the ECAN module is
unable to switch from Listen Only mode directly to
Configuration mode.
Work around
Use the REQOP (CANCON<7:5>) bits to select
Normal mode as an intermediate step when
switching from Listen Only mode to Configuration
mode.
Date Codes that pertain to this issue:
All engineering and production devices.
Under specific conditions, the TXBxSIDH register
of the pending message for transmission may be
corrupted. The following conditions must exist for
this event to occur:
1. A transmit message must be pending.
2. All of the receive buffers must be full and a
3. A receiver buffer must be made available
Work around
Ensure that a receive buffer overflow condition
does not occur and/or ensure that a transmit
request is not pending if a receive buffer overflow
condition does exist.
The pseudo-code segment in Example 6 is an
example of how to disable a pending transmission.
This code is for illustration purposes only.
Date Codes that pertain to this issue:
All engineering and production devices.
received message is in the Message Assembly
Buffer (MAB).
(RXBxCON<RXFUL> set to '0') when a Start-
of-Frame (SOF) is recognized on the CAN bus,
or on the instruction cycle prior to the SOF for
the TXBxSIDH corruption event to occur. The
timing of this event is crucial.
DS80283E-page 9