PIC18F6620T-I/PT Microchip Technology, PIC18F6620T-I/PT Datasheet - Page 297

• Manufacturer Part Number: PIC18F6620T-I/PT
• Description: IC MCU FLASH 32KX16 W/AD 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6620T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.75K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3840 B
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 2 x 8 bit
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Data Rom Size: 1024 B
• Height: 1 mm
• Length: 10 mm
• Supply Voltage (max): 5.5 V, 5.8 V
• Supply Voltage (min): 3.9 V, 4.2 V
• Width: 10 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SUBLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example 1:
Example 2:
Example 3:
 2004 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
W
C
W
C
Z
N
W
C
W
C
Z
N
W
C
W
C
Z
N
Q1
PIC18F6520/8520/6620/8620/6720/8720
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
literal ‘k’
[ label ] SUBLW k
0
k – (W)
N, OV, C, DC, Z
W is subtracted from the eight-bit
literal ‘k’. The result is placed in
W.
1
1
SUBLW
SUBLW
SUBLW
Subtract W from literal
Read
Q2
0000
1
?
1
1
0
0
2
?
0
1
1
0
3
?
FF ; (2’s complement)
0
0
1
k
; result is positive
; result is zero
; result is negative
255
0x02
0x02
0x02
1000
W
Process
Data
Q3
kkkk
Write to W
Q4
kkkk
SUBWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example 1:
Example 2:
Example 3:
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
REG
W
C
REG
W
C
Z
N
REG
W
C
REG
W
C
Z
N
REG
W
C
REG
W
C
Z
N
Q1
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
register ‘f’
Subtract W from f
[ label ] SUBWF
0
d
a
(f) – (W)
N, OV, C, DC, Z
Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’,
the result is stored in W. If ‘d’ is
‘1’, the result is stored back in
register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ is
‘1’, then the bank will be selected
as per the BSR value (default).
1
1
SUBWF
SUBWF
SUBWF
Read
Q2
0101
3
2
?
1
2
1
0
0
2
2
?
2
0
1
1
0
1
2
?
FFh ;(2’s complement)
2
0
0
1
f
[0,1]
[0,1]
255
; result is positive
; result is zero
; result is negative
REG, 1, 0
REG, 0, 0
REG, 1, 0
11da
dest
Process
Data
Q3
DS39609B-page 295
ffff
f [,d [,a]
destination
Write to
Q4
ffff