DSPIC30F6011A-20E/PF Microchip Technology, DSPIC30F6011A-20E/PF Datasheet - Page 139
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DSPIC30F6011A-20E/PF
Manufacturer Part Number
DSPIC30F6011A-20E/PF
Description
IC DSPIC MCU/DSP 132K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F6011A-30IPT.pdf
(234 pages)
4.DSPIC30F6011A-30IPT.pdf
(8 pages)
5.DSPIC30F6011A-30IPT.pdf
(10 pages)
6.DSPIC30F6011A-30IPT.pdf
(6 pages)
7.DSPIC30F6011A-30IPT.pdf
(8 pages)
8.DSPIC30F6011A-30IPT.pdf
(16 pages)
9.DSPIC30F6011A-30IPF.pdf
(236 pages)
Specifications of DSPIC30F6011A-20E/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
132KB (44K x 24)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TQFP, 64-VQFP
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
52
Flash Memory Size
132KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6011A-20E/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
19.9
The module has 2 internal Power modes.
When the ADON bit is ‘1’, the module is in Active mode;
it is fully powered and functional.
When ADON is ‘0’, the module is in Off mode. The dig-
ital and analog portions of the circuit are disabled for
maximum current savings.
In order to return to the Active mode from Off mode, the
user must wait for the ADC circuitry to stabilize.
19.10 ADC Operation During CPU Sleep
19.10.1
When the device enters Sleep mode, all clock sources
to the module are shutdown and stay at logic ‘0’.
If Sleep occurs in the middle of a conversion, the con-
version is aborted. The converter will not continue with
a partially completed conversion on exit from Sleep
mode.
Register contents are not affected by the device
entering or leaving Sleep mode.
The ADC module can operate during Sleep mode if the
ADC clock source is set to RC (ADRC = 1). When the
RC clock source is selected, the ADC module waits one
instruction cycle before starting the conversion. This
allows the SLEEP instruction to be executed which elim-
inates all digital switching noise from the conversion.
When the conversion is complete, the CONV bit will be
cleared and the result loaded into the ADCBUF register.
FIGURE 19-5:
© 2011 Microchip Technology Inc.
RAM Contents:
Read to Bus:
Module Power-down Modes
and Idle Modes
Signed Fractional
ADC OPERATION DURING CPU
SLEEP MODE
Signed Integer
Fractional
Integer
ADC OUTPUT DATA FORMATS
dsPIC30F6011A/6012A/6013A/6014A
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
d11 d11 d11 d11 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
0
0
0
0
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
If the ADC interrupt is enabled, the device will wake-up
from Sleep. If the ADC interrupt is not enabled, the
ADC module will then be turned off, although the
ADON bit will remain set.
19.10.2
The ADSIDL bit selects if the module will stop on Idle or
continue on Idle. If ADSIDL = 0, the module will con-
tinue operation on assertion of Idle mode. If ADSIDL =
1, the module will stop on Idle.
19.11 Effects of a Reset
A device Reset forces all registers to their Reset state.
This forces the ADC module to be turned off, and any
conversion and sampling sequence is aborted. The val-
ues that are in the ADCBUF registers are not modified.
The ADC Result register will contain unknown data
after a Power-on Reset.
19.12 Output Formats
The ADC result is 12 bits wide. The data buffer RAM is
also 12 bits wide. The 12-bit data can be read in one of
four different formats. The FORM<1:0> bits select the
format. Each of the output formats translates to a 16-bit
result on the data bus.
ADC OPERATION DURING CPU
IDLE MODE
0
0
DS70143E-page 139
0
0
0
0
0
0