AT89C51AC3-RLTUM Atmel, AT89C51AC3-RLTUM Datasheet - Page 92

IC 8051 MCU FLASH 64K 44VQFP

AT89C51AC3-RLTUM

Manufacturer Part Number
AT89C51AC3-RLTUM
Description
IC 8051 MCU FLASH 64K 44VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet

Specifications of AT89C51AC3-RLTUM

Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Interface Type
UART, SPI
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
36
Number Of Timers
3
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
89C
Device Core
8051
Device Core Size
8b
Frequency (max)
60MHz
Total Internal Ram Size
2.25KB
# I/os (max)
36
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
VQFP
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89C51AC3-RLTUM
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT89C51AC3-RLTUM
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Serial Peripheral Status Register
and Control (SPSCR)
92
AT89C51AC3
Reset Value = 0001 0100b
Not bit addressable
The Serial Peripheral Status Register contains flags to signal the following conditions:
Table 49. SPSCR Register
SPSCR - Serial Peripheral Status and Control register (0D5H)
Bit Number
Number
SPIF
Data transfer complete
Write collision
Inconsistent logic level on SS pin (mode fault error)
Bit
7
7
6
5
3
2
1
0
Mnemonic Description
SPIF
OVR
Bit
Bit Mnemonic
6
-
-
CPOL
CPHA
SPR1
SPR0
Serial Peripheral Data Transfer Flag
Cleared by hardware to indicate data transfer is in progress or has been
approved by a clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
This bit is cleared when reading or writing SPDATA after reading SPSCR.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Overrun Error Flag
- Set by hardware when a byte is received whereas SPIF is set (the previous
received data is not overwritten).
- Cleared by hardware when reading SPSCR
OVR
5
Description
Clock Polarity
Cleared to have the SCK set to ’0’ in idle state.
Set to have the SCK set to ’1’ in idle state.
Clock Phase
Cleared to have the data sampled when the SCK leaves the idle
state (see CPOL).
Set to have the data sampled when the SCK returns to idle state (see
CPOL).
SPR2
0
0
0
0
1
1
1
1
MODF
4
SPR1
0
0
1
1
0
0
1
1
SPR0 Serial Peripheral Rate
SPTE
0
1
0
1
0
1
0
1
3
Invalid
F
F
F
F
F
F
Invalid
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
UARTM
2
/4
/8
/16
/32
/64
/128
4383D–8051–02/08
SPTEIE
1
MODFIE
0

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