PIC32MX575F512L-80I/PF Microchip Technology, PIC32MX575F512L-80I/PF Datasheet - Page 83

• Manufacturer Part Number: PIC32MX575F512L-80I/PF
• Description: IC MCU 32BIT 512KB FLASH 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX575F512L-80I/PF

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: CAN, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Controller Family/series: PIC32
• Ram Memory Size: 64KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Interface: CAN, I2C, SPI, UART, USB
• No. Of Pwm Channels: 5
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: PIC32MX5xx
• Core: MIPS
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 4-17:
TABLE 4-18:
Legend:
Note
Legend:
Note
3000 DMACON
3010
3020 DMAADDR
3030 DCRCCON
3040 DCRCDATA
3050 DCRCXOR
1:
1:
DMASTAT
2:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See
DMACH<3> bit is not available on PIC32MX534/564/664/764 devices.
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
(1)
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
DMA GLOBAL REGISTER MAP
DMA CRC REGISTER MAP
31/15
31/15
ON
—
—
—
—
—
30/14
FRZ
30/14
—
—
—
—
—
29/13
29/13
—
—
—
—
—
BYTO<1:0>
SUSPEND DMABUSY
28/12
28/12
—
—
—
(1)
27/11
27/11
WBO
—
—
—
PLEN<4:0>
26/10
26/10
—
—
—
—
—
25/9
25/9
—
—
—
—
—
DMAADDR<31:0>
DCRCDATA<31:0>
DCRCXOR<31:0>
24/8
BITO
24/8
—
—
—
—
Bits
Bits
CRCEN
23/7
23/7
—
—
—
—
—
CRCAPP
22/6
22/6
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
CRCTYP
21/5
21/5
—
—
—
—
—
20/4
20/4
Section 12.1.1 “CLR, SET and INV Registers”
—
—
—
—
—
—
RDWR
19/3
19/3
—
—
—
—
—
18/2
18/2
—
—
—
—
DMACH<2:0>
CRCCH<2:0>
for more information.
17/1
17/1
—
—
—
—
(2)
for more
16/0
16/0
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000