PIC18C658-E/L Microchip Technology, PIC18C658-E/L Datasheet - Page 156
![IC MCU OTP 16KX16 CAN 68PLCC](/photos/12/13/121323/c04-049_l_sml.jpg)
PIC18C658-E/L
Manufacturer Part Number
PIC18C658-E/L
Description
IC MCU OTP 16KX16 CAN 68PLCC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C658-IPT.pdf
(366 pages)
4.PIC18C658-IPT.pdf
(16 pages)
5.PIC18C658-IPT.pdf
(16 pages)
6.PIC18C658-IPT.pdf
(16 pages)
Specifications of PIC18C658-E/L
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
68-PLCC
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
3-Wire, I2C, SPI, USART, CAN
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
52
Number Of Timers
4 bit
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
ICE2000, DM163007, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
6
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA18XL680 - ADAPTER DEVICE ICE 68PLCCAC174007 - MODULE SKT PROMATEII 68PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18C658E/L
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C658-E/L
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C658-IPT PDF datasheet #3
- PIC18C658-IPT PDF datasheet #4
- PIC18C658-IPT PDF datasheet #5
- PIC18C658-IPT PDF datasheet #6
- Current page: 156 of 366
- Download datasheet (7Mb)
PIC18CXX8
15.4.8
Transmission of a data byte, a 7-bit address, or the
other half of a 10-bit address, is accomplished by sim-
ply writing a value to the SSPBUF register. This action
will set the Buffer Full bit, BF, and allow the baud rate
generator to begin counting and start the next transmis-
sion. Each bit of address/data will be shifted out onto
the SDA pin after the falling edge of SCL is asserted
(see data hold time specification parameter 106). SCL
is held low for one baud rate generator roll over count
(T
high (see data setup time specification parameter 107).
When the SCL pin is released high, it is held that way
for T
for that duration and some hold time after the next fall-
ing edge of SCL. After the eighth bit is shifted out (the
falling edge of the eighth clock), the BF bit is cleared
and the master releases SDA, allowing the slave
device being addressed to respond with an ACK bit
during the ninth bit time if an address match occurs, or
if data was received properly.
written into the ACKDT bit on the falling edge of the
ninth clock. If the master receives an acknowledge, the
Acknowledge Status bit, ACKSTAT, is cleared. If not,
the bit is set. After the ninth clock, the SSPIF bit is set
and the master clock (baud rate generator) is sus-
pended until the next data byte is loaded into the SSP-
BUF,
(Figure 15-15).
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL, until all seven
address bits and the R/W bit, are completed. On the
falling edge of the eighth clock, the master will
de-assert the SDA pin, allowing the slave to respond
with an acknowledge. On the falling edge of the ninth
clock, the master will sample the SDA pin to see if the
address was recognized by a slave. The status of the
ACK bit is loaded into the ACKSTAT status bit
(SSPCON2 register). Following the falling edge of the
ninth clock transmission of the address, the SSPIF is
set, the BF bit is cleared and the baud rate generator is
turned off, until another write to the SSPBUF takes
place, holding SCL low and allowing SDA to float.
15.4.8.1
In Transmit mode, the BF bit (SSPSTAT register) is set
when the CPU writes to SSPBUF, and is cleared when
all eight bits are shifted out.
DS30475A-page 156
BRG
BRG
). Data should be valid before SCL is released
leaving
. The data on the SDA pin must remain stable
I
2
C MASTER MODE TRANSMISSION
BF Status Flag
SCL
low
and
The status of ACK is
SDA
Advanced Information
unchanged
15.4.8.2
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
15.4.8.3
In Transmit mode, the ACKSTAT bit (SSPCON2
register) is cleared when the slave has sent an
acknowledge (ACK = 0), and is set when the slave
does not acknowledge (ACK = 1). A slave sends an
acknowledge when it has recognized its address
(including a general call), or when the slave has
properly received its data.
15.4.9
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPCON2 register).
The baud rate generator begins counting, and on each
rollover, the state of the SCL pin changes (high to
low/low to high) and data is shifted into the SSPSR.
After the falling edge of the eighth clock, the RCEN bit
is automatically cleared, the contents of the SSPSR are
loaded into the SSPBUF, the BF bit is set, the SSPIF
flag bit is set and the baud rate generator is suspended
from counting, holding SCL low. The MSSP is now in
IDLE state, awaiting the next command. When the
buffer is read by the CPU, the BF bit is automatically
cleared. The user can then send an Acknowledge bit at
the end of reception, by setting the Acknowledge
Sequence Enable bit ACKEN (SSPCON2 register).
15.4.9.1
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
15.4.9.2
In receive operation, the SSPOV bit is set when eight
bits are received into the SSPSR and the BF bit is
already set from a previous reception.
15.4.9.3
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
Note:
I
2
C MASTER MODE RECEPTION
WCOL Status Flag
ACKSTAT Status Flag
The MSSP module must be in an IDLE
state before the RCEN bit is set, or the
RCEN bit will be disregarded.
BF Status Flag
SSPOV Status Flag
WCOL Status Flag
2000 Microchip Technology Inc.
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