PIC18C858-E/PT Microchip Technology, PIC18C858-E/PT Datasheet - Page 70

• Manufacturer Part Number: PIC18C858-E/PT
• Description: IC MCU OTP 16KX16 CAN 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C858-E/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: 3-Wire, I2C, SPI, USART, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 68
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163007, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6
• Data Rom Size: 4 KB
• Height: 1 mm
• Length: 12 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.2 V
• Width: 12 mm
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C858E/PT

PIC18CXX8
5.2.3
The long write must be terminated by a RESET or any
interrupt.
The interrupt source must have its interrupt enable bit
set. When the source sets its interrupt flag, program-
ming will terminate. This will occur regardless of the
settings of interrupt priority bits, the GIE/GIEH bit or the
PIE/GIEL bit.
Depending on the states of interrupt priority bits, the
GIE/GIEH bit or the PIE/GIEL bit, program execution
can either be vectored to the high or low priority Inter-
rupt Service Routine (ISR), or continue execution from
where programming commenced.
In either case, the interrupt flag will not be cleared
when programming is terminated and will need to be
cleared by the software.
TABLE 5-2:
DS30475A-page 70
(default)
(default)
(default)
GIEH
GIE/
X
X
0
0
1
0
1
LONG WRITE INTERRUPTS
(default)
(default)
(default)
GIEL
PIE/
X
X
0
1
0
1
0
SLEEP MODE, INTERRUPT ENABLE BITS AND INTERRUPT RESULTS
high priority
high priority
(default)
(default)
Priority
low
low
X
X
X
1
0
0
1
Interrupt
(default)
Advanced Information
Enable
0
1
1
1
1
1
1
Interrupt
Flag
X
0
1
1
1
1
1
5.3
If a write is terminated by an unplanned event such as
loss of power, an unexpected RESET, or an interrupt
that was not disabled, the memory location just pro-
grammed should be verified and reprogrammed if
needed.
Long write continues even if interrupt flag
becomes set during SLEEP.
Long write continues, will wake when
the interrupt flag is set.
Terminates long write, executes next instruction.
Interrupt flag not cleared.
Terminates long write, executes next instruction.
Interrupt flag not cleared.
Terminates long write, executes next instruction.
Interrupt flag not cleared.
Terminates long write, branches to low priority
interrupt vector.
Interrupt flag can be cleared by ISR.
Terminates long write, branches to high priority
interrupt vector.
Interrupt flag can be cleared by ISR.
Unexpected Termination of Write
Operations
 2000 Microchip Technology Inc.
Action