ATMEGA64L-8MQ Atmel, ATMEGA64L-8MQ Datasheet - Page 380
ATMEGA64L-8MQ
Manufacturer Part Number
ATMEGA64L-8MQ
Description
IC MCU AVR 64K FLASH 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA64L-8MQ
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
2-Wire, JTAG, SPI, USART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
53
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 380 of 392
- Download datasheet (8Mb)
2490Q–AVR–06/10
4. Stabilizing time needed when changing OSCCAL Register
5. IDCODE masks data from TDI input
6. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt
After increasing the source clock frequency more than 2% with settings in the OSCCAL reg-
ister, the device may execute some of the subsequent instructions incorrectly.
Problem Fix / Workaround
The behavior follows errata number 3., and the same Fix / Workaround is applicable on this
errata.
The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are
replaced by all-ones during Update-DR.
Problem Fix / Workaround
–
–
–
request.
Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR reg-
ister triggers an unexpected EEPROM interrupt request.
Problem Fix / Workaround
Always use OUT or SBI to set EERE in EECR.
If ATmega64 is the only device in the scan chain, the problem is not visible.
Select the Device ID Register of the ATmega64 by issuing the IDCODE instruction or
by entering the Test-Logic-Reset state of the TAP controller to read out the contents
of its Device ID Register and possibly data from succeeding devices of the scan
chain. Issue the BYPASS instruction to the ATmega64 while reading the Device ID
Registers of preceding devices of the boundary scan chain.
If the Device IDs of all devices in the boundary scan chain must be captured
simultaneously, the ATmega64 must be the first device in the chain.
ATmega64(L)
380
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